[coreboot-gerrit] New patch to review for coreboot: Kconfig: Get rid of obsolete CAR_MIGRATION symbols
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Sun Jun 21 01:16:05 CEST 2015
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10616
-gerrit
commit ddb86c172d70d443e4e1f734a6ed00b82280e3d9
Author: Martin Roth <gaumless at gmail.com>
Date: Sat Jun 20 16:40:28 2015 -0600
Kconfig: Get rid of obsolete CAR_MIGRATION symbols
CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION
CACHE_ROM is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless at gmail.com>
---
src/mainboard/google/auron/Kconfig | 1 -
src/mainboard/intel/mohonpeak/Kconfig | 1 -
src/soc/intel/baytrail/Kconfig | 1 -
src/soc/intel/braswell/Kconfig | 1 -
src/soc/intel/broadwell/Kconfig | 2 -
src/southbridge/intel/common/firmware/Kconfig | 94 ++++++++++++++++++++++
src/southbridge/intel/common/firmware/Makefile.inc | 73 +++++++++++++++++
7 files changed, 167 insertions(+), 6 deletions(-)
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 779e6b3..4693d04 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
- select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select CHROMEOS_RAMOOPS_DYNAMIC
select INTEL_INT15
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 2aaa766..f487e2b 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select MMCONF_SUPPORT
select POST_IO
- select DEFAULT_POST_DEVICE_LPC
select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
config MAINBOARD_DIR
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5060e45..cbf4a1f 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select BACKUP_DEFAULT_SMM_REGION
select CACHE_MRC_SETTINGS
- select CAR_MIGRATION
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index aa191b3..a7bc046 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select BACKUP_DEFAULT_SMM_REGION
select CACHE_MRC_SETTINGS
- select CAR_MIGRATION
select COLLECT_TIMESTAMPS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 1ef386b..84f25f0 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -18,8 +18,6 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_MRC_SETTINGS
select MRC_SETTINGS_PROTECT
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
- select CACHE_ROM
- select CAR_MIGRATION
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_MONOTONIC_TIMER
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
new file mode 100644
index 0000000..1f4d935
--- /dev/null
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -0,0 +1,94 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+config HAVE_INTEL_FIRMWARE
+ bool
+ help
+ Chipset uses the Intel Firmware Descriptor to describe the
+ layout of the SPI ROM chip.
+
+if HAVE_INTEL_FIRMWARE
+
+comment "Intel Firmware"
+
+config HAVE_IFD_BIN
+ bool "Add Intel descriptor.bin file"
+ help
+ The descriptor binary
+
+config IFD_BIN_PATH
+ string "Path and filename of the descriptor.bin file"
+ depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
+
+config HAVE_ME_BIN
+ bool "Add Intel Management Engine firmware"
+ depends on USES_INTEL_ME && HAVE_IFD_BIN
+ help
+ The Intel processor in the selected system requires a special firmware
+ for an integrated controller called Management Engine (ME). The ME
+ firmware might be provided in coreboot's 3rdparty/blobs repository. If
+ not and if you don't have the firmware elsewhere, you can still
+ build coreboot without it. In this case however, you'll have to make
+ sure that you don't overwrite your ME firmware on your flash ROM.
+
+config ME_BIN_PATH
+ string "Path to management engine firmware"
+ depends on HAVE_ME_BIN
+
+##### Fake IFD #####
+
+config BUILD_WITH_FAKE_IFD
+ bool "Build with a fake IFD" if !HAVE_IFD_BIN
+ help
+ If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
+ board, you can select this option and coreboot will build without it.
+ The resulting coreboot.rom will not contain all parts required
+ to get coreboot running on your board. You can however write only the
+ BIOS section to your board's flash ROM and keep the other sections
+ untouched. Unfortunately the current version of flashrom doesn't
+ support this yet. But there is a patch pending [1].
+
+ WARNING: Never write a complete coreboot.rom to your flash ROM if it
+ was built with a fake IFD. It just won't work.
+
+ [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+
+config IFD_BIOS_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+config IFD_ME_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+config IFD_GBE_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+config IFD_PLATFORM_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+
+endif #INTEL_FIRMWARE
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
new file mode 100644
index 0000000..c79a1df
--- /dev/null
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -0,0 +1,73 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y)
+
+# Run intermediate steps when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+
+ifeq ($(CONFIG_HAVE_IFD_BIN),y)
+INTERMEDIATE+=add_intel_firmware
+endif
+
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+INTERMEDIATE+=add_intel_firmware_descriptor
+IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
+IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
+ $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
+ $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
+ $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
+else
+IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
+endif
+
+add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+ printf "\n** WARNING **\n"
+ printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
+ printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
+ printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
+ printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
+ $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
+endif
+ printf " DD Adding Intel Firmware Descriptor\n"
+ dd if=$(IFD_BIN_PATH) \
+ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ifeq ($(CONFIG_HAVE_ME_BIN),y)
+ printf " IFDTOOL me.bin -> coreboot.pre\n"
+ $(objutil)/ifdtool/ifdtool \
+ -i ME:$(CONFIG_ME_BIN_PATH) \
+ $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+ printf " IFDTOOL Locking Management Engine\n"
+ $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+ printf " IFDTOOL Unlocking Management Engine\n"
+ $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+
+PHONY+=add_intel_firmware
+
+endif
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