[coreboot-gerrit] New patch to review for coreboot: Skylake:Set DISB inside romstage after mrc init

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11550

-gerrit

commit 91722e80f765821ac5b32e3a77f7f5554c424091
Author: Dhaval Sharma <dhaval.v.sharma at intel.com>
Date:   Thu Aug 27 17:13:19 2015 +0530

    Skylake:Set DISB inside romstage after mrc init
    
    Set DISB inside romstage right after successful mrc init such that
    any reset events afterwards can take fast boot path and in turn
    achieve better boot performance
    
    BRANCH=NONE
    BUG=chrome-os-partner:43637
    TEST=Built for kunimitsu and tested DISB is set correctly and fast
    boot path is taken.
    
    Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
    Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
    Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295509
    Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Tested-by: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/pmc.c               |  2 --
 src/soc/intel/skylake/romstage/romstage.c | 17 +++++++++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 2704956..fb09589 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -47,8 +47,6 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
 			DIS_SLP_X_STRCH_SUS_UP),
 	/* Enable SCI and clear SLP requests. */
 	REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
-	/* Indicate DRAM init done for MRC */
-	REG_PCI_OR32(GEN_PMCON_A, DISB),
 	REG_SCRIPT_END
 };
 
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 91a496e..6c5d64a 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -30,6 +30,7 @@
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <reset.h>
@@ -37,6 +38,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>
+#include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/romstage.h>
 #include <soc/spi.h>
@@ -405,3 +407,18 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
 	soc_display_upd_value("RMT", 1, old->RMT, new->RMT);
 }
+
+/* SOC initialization after RAM is enabled. */
+void soc_after_ram_init(struct romstage_params *params)
+{
+	/* Set the DISB as soon as possible after DRAM
+	 * init and MRC cache is saved.
+	 */
+	u32 disb_val = 0;
+	device_t dev = PCH_DEV_PMC;
+	disb_val = pci_read_config32(dev, GEN_PMCON_A);
+	disb_val |= DISB;
+	/* Preserve bits which get cleared up if written 1 */
+	disb_val &= ~(GBL_RST_STS | MS4V);
+	pci_write_config32(dev, GEN_PMCON_A, disb_val);
+}