[coreboot-gerrit] New patch to review for coreboot: intel/common: Print board ID if enabled

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11577

-gerrit

commit ccdb90ba383a3249d61284a6a7442bfef8cec3d3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Sep 4 13:47:34 2015 -0700

    intel/common: Print board ID if enabled
    
    Read and print the board ID if it is enabled in the mainboard.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f
    Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297756
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/common/romstage.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index 7a05e17..ee9c975 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -25,6 +25,7 @@
 #include <arch/cbfs.h>
 #include <arch/stages.h>
 #include <arch/early_variables.h>
+#include <boardid.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
@@ -101,6 +102,13 @@ asmlinkage void *romstage_main(unsigned int bist,
 	/* Perform SOC specific initialization. */
 	soc_romstage_init(&params);
 
+	/*
+	 * Read and print board version.  Done after SOC romstage
+	 * in case PCH needs to be configured to talk to the EC.
+	 */
+	if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
+		printk(BIOS_INFO, "MLB: board version %d\n", board_id());
+
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&params);
 	soc_after_ram_init(&params);