[coreboot-gerrit] Patch merged into coreboot/master: riscv-memlayout: fix existing memlayout issues, add sbi interface

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a47738d10f9c6e4d14ffbd35a01c6e70c2c494e5
Author: Thaminda Edirisooriya <thaminda at google.com>
Date:   Wed Aug 26 15:39:16 2015 -0700

    riscv-memlayout: fix existing memlayout issues, add sbi interface
    
    Existing memlayout code placed sections in overlapping areas, and would
    overwrite the payload if it was large enough. Update memlayout.ld in
    src/mainboard/emulation/spike-riscv to represent the spike emulator, and
    add sbi interface which now has room into src/arch/riscv/bootblock.S.
    Add utility code to qemu-riscv, but emulator itself has yet to be
    updated to new ISA and as such should not be used.
    Update Makefile to include all the files necessary for sbi interface.
    
    Clean up unused include in src/arch/riscv/include/atomic.h and
    whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
    Fixed whitespace issues in spike_util.c
    
    Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
    Signed-off-by: Thaminda Edirisooriya <thaminda at google.com>
    Reviewed-on: http://review.coreboot.org/11370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/11370 for details.

-gerrit