[coreboot-gerrit] New patch to review for coreboot: google/reef: Enable I2C2 for use in bootblock

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16059

-gerrit

commit cf31e5e628faade3564382cd1f99ef7a6fc42f0a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Aug 3 17:15:02 2016 -0700

    google/reef: Enable I2C2 for use in bootblock
    
    Enable I2C bus 2 for early init so it can be used by vboot for TPM
    communication for verifying the memory init code.
    
    BUG=chrome-os-partner:53336
    BRANCH=none
    TEST=build and boot on reef
    
    Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/reef/devicetree.cb | 3 +++
 src/mainboard/google/reef/gpio.h        | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index 5e68d37..ea3b20f 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -43,6 +43,9 @@ chip soc/intel/apollolake
 	register "gpe0_dw2" = "PMC_GPE_N_63_32"
 	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
 
+	# Enable I2C2 bus early for TPM access
+	register "i2c[2].early_init" = "1"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index 1e88215..b452c22 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -340,6 +340,9 @@ static const struct pad_config gpio_table[] = {
 /* GPIOs needed prior to ramstage. */
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),	 /* I2S1_BCLK -- PCH_WP */
+	/* I2C2 - TPM  */
+	PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
+	PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
 };
 
 /*