[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Switch to using serial routines for FSP
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Sat Aug 6 19:00:03 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16105
-gerrit
commit 093ce9a11e3325c2964e4ec7cac8a57636843557
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sat Aug 6 09:51:35 2016 -0700
soc/intel/quark: Switch to using serial routines for FSP
Switch from passing FSP the serial port address to passing FSP the
serial port output routine. This enables coreboot to use any UART in
the system and also log the FSP output.
TEST=Build and run on Galileo Gen2
Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/include/soc/fsp/FspmUpd.h | 14 +++++++-
src/soc/intel/quark/include/soc/uart.h | 39 +++++++++++++++++++++++
src/soc/intel/quark/romstage/fsp1_1.c | 18 +++++++----
src/soc/intel/quark/romstage/fsp2_0.c | 6 ++--
src/soc/intel/quark/uart_common.c | 20 ++++++++++++
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 21 ++++++++----
6 files changed, 102 insertions(+), 16 deletions(-)
diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
index bb0fc51..a7a54a8 100644
--- a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
+++ b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
@@ -53,7 +53,7 @@ struct FSP_M_CONFIG {
/** Offset 0x0048 - SerialPortBaseAddress
Debug serial port base address set by BIOS. Zero disables debug serial output.
**/
- uint32_t SerialPortBaseAddress;
+ uint32_t Reserved_48;
/** Offset 0x004C - tRAS
ACT to PRE command period in picoseconds.
@@ -200,6 +200,18 @@ struct FSP_M_CONFIG {
/** Offset 0x0080
**/
+ uint32_t SerialPortPollForChar;
+
+/** Offset 0x0084
+**/
+ uint32_t SerialPortReadChar;
+
+/** Offset 0x0088
+**/
+ uint32_t SerialPortWriteChar;
+
+/** Offset 0x008C
+**/
uint16_t UpdTerminator;
} __attribute__((packed));
diff --git a/src/soc/intel/quark/include/soc/uart.h b/src/soc/intel/quark/include/soc/uart.h
new file mode 100644
index 0000000..a5cc7e4
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/uart.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_UART_H_
+#define _SOC_UART_H_
+
+#include <stddef.h>
+
+/*
+ * Write data from buffer to serial device.
+ *
+ * Writes number_of_bytes data bytes from Buffer to the serial device.
+ * The number of bytes actually written to the serial device is returned.
+ *
+ * If number_of_bytes is zero, don't output any data but instead wait until
+ * the serial port has output all data, then return 0.
+ *
+ * @param buffer Pointer to the data buffer to be written.
+ * @param number_of_bytes Number of bytes to written to the serial device.
+ *
+ * @retval 0 number_of_bytes is 0.
+ * @retval >0 The number of bytes written to the serial device.
+ */
+__attribute__((cdecl)) unsigned long uart_write_char(uint8_t *buffer,
+ size_t number_of_bytes);
+
+#endif /* _SOC_UART_H_ */
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index 5ba2174..5708bf4 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -21,10 +21,10 @@
#include "../chip.h"
#include <fsp/memmap.h>
#include <fsp/util.h>
-#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/QuarkNcSocId.h>
#include <soc/romstage.h>
+#include <soc/uart.h>
#include <string.h>
asmlinkage void *car_stage_c_entry(void)
@@ -120,8 +120,8 @@ void soc_memory_init_params(struct romstage_params *params,
upd->RankMask = config->RankMask;
upd->RmuBaseAddress = (uintptr_t)rmu_file;
upd->RmuLength = rmu_file_len;
- upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
- ? UART_BASE_ADDRESS : 0;
+ upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
+ ? (uint32_t)(uintptr_t)uart_write_char : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
config->SmmTsegSize : 0;
upd->SocRdOdtVal = config->SocRdOdtVal;
@@ -176,9 +176,15 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
old->RmuBaseAddress, new->RmuBaseAddress);
fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
old->RmuLength, new->RmuLength);
- fsp_display_upd_value("SerialPortBaseAddress",
- sizeof(old->SerialPortBaseAddress),
- old->SerialPortBaseAddress, new->SerialPortBaseAddress);
+ fsp_display_upd_value("SerialPortPollForChar",
+ sizeof(old->SerialPortPollForChar),
+ old->SerialPortPollForChar, new->SerialPortPollForChar);
+ fsp_display_upd_value("SerialPortReadChar",
+ sizeof(old->SerialPortReadChar),
+ old->SerialPortReadChar, new->SerialPortReadChar);
+ fsp_display_upd_value("SerialPortWriteChar",
+ sizeof(old->SerialPortWriteChar),
+ old->SerialPortWriteChar, new->SerialPortWriteChar);
fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
old->SmmTsegSize, new->SmmTsegSize);
fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 6ca6a4c..f80e9aa 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -20,11 +20,11 @@
#include "../chip.h"
#include <cpu/x86/cache.h>
#include <fsp/util.h>
-#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/reg_access.h>
+#include <soc/uart.h>
asmlinkage void *car_stage_c_entry(void)
{
@@ -161,8 +161,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd)
upd->RankMask = config->RankMask;
upd->RmuBaseAddress = (uintptr_t)rmu_file;
upd->RmuLength = rmu_file_len;
- upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
- ? UART_BASE_ADDRESS : 0;
+ upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
+ ? (uint32_t)(uintptr_t)uart_write_char : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
config->SmmTsegSize : 0;
upd->SocRdOdtVal = config->SocRdOdtVal;
diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c
index 4408d87..f6be2d7 100644
--- a/src/soc/intel/quark/uart_common.c
+++ b/src/soc/intel/quark/uart_common.c
@@ -15,8 +15,10 @@
* GNU General Public License for more details.
*/
+#include <console/streams.h>
#include <console/uart.h>
#include <soc/iomap.h>
+#include <soc/uart.h>
unsigned int uart_platform_refclk(void)
{
@@ -27,3 +29,21 @@ uintptr_t uart_platform_base(int idx)
{
return UART_BASE_ADDRESS;
}
+
+__attribute__((cdecl)) unsigned long uart_write_char(uint8_t *buffer,
+ size_t number_of_bytes)
+{
+ uint8_t *buffer_end;
+
+ /* Finish displaying all of the serial data if requested */
+ if (number_of_bytes == 0) {
+ console_tx_flush();
+ return 0;
+ }
+
+ /* Output the serial data */
+ buffer_end = &buffer[number_of_bytes];
+ while (buffer_end > buffer)
+ console_tx_byte(*buffer++);
+ return number_of_bytes;
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
index 2c7e812..168cda1 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -91,7 +91,7 @@ typedef struct {
UINT32 RmuLength;
/** Offset 0x0030
**/
- UINT32 SerialPortBaseAddress;
+ UINT32 Reserved_30;
/** Offset 0x0034
**/
UINT32 tRAS;
@@ -178,17 +178,26 @@ typedef struct {
UINT32 MrcDataLength;
/** Offset 0x0068
**/
- UINT8 ReservedMemoryInitUpd[8];
+ UINT32 SerialPortPollForChar;
+/** Offset 0x006C
+**/
+ UINT32 SerialPortReadChar;
+/** Offset 0x0070
+**/
+ UINT32 SerialPortWriteChar;
+/** Offset 0x0074
+**/
+ UINT8 ReservedMemoryInitUpd[12];
} MEMORY_INIT_UPD;
typedef struct {
-/** Offset 0x0070
+/** Offset 0x0080
**/
UINT64 Signature;
-/** Offset 0x0078
+/** Offset 0x0088
**/
UINT64 Revision;
-/** Offset 0x0080
+/** Offset 0x0090
**/
UINT16 PcdRegionTerminator;
} SILICON_INIT_UPD;
@@ -213,7 +222,7 @@ typedef struct _UPD_DATA_REGION {
/** Offset 0x0018
**/
MEMORY_INIT_UPD MemoryInitUpd;
-/** Offset 0x0070
+/** Offset 0x0080
**/
SILICON_INIT_UPD SiliconInitUpd;
} UPD_DATA_REGION;
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