[coreboot-gerrit] New patch to review for coreboot: mainboard/google/rush: remove rush mainboard
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Sat Aug 6 20:46:01 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16106
-gerrit
commit e887a3c11adc9f28b0b1b572d76a6be1683b3d6b
Author: Aaron Durbin <adurbin at chromium.org>
Date: Sat Aug 6 13:40:11 2016 -0500
mainboard/google/rush: remove rush mainboard
The rush board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
Change-Id: I0f77bb791491509da7bd9cf25050e01c2f734a2f
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/rush/Kconfig | 98 -------
src/mainboard/google/rush/Kconfig.name | 2 -
src/mainboard/google/rush/Makefile.inc | 47 ----
src/mainboard/google/rush/bct/Makefile.inc | 23 --
src/mainboard/google/rush/bct/cfg2inc.sh | 30 --
src/mainboard/google/rush/bct/emmc.cfg | 13 -
src/mainboard/google/rush/bct/jtag.cfg | 16 --
src/mainboard/google/rush/bct/odmdata.cfg | 1 -
.../google/rush/bct/sdram-hynix-2GB-792.inc | 311 ---------------------
.../google/rush/bct/sdram-hynix-2GB-924.inc | 311 ---------------------
.../google/rush/bct/sdram-hynix-4GB-300.inc | 311 ---------------------
.../google/rush/bct/sdram-hynix-4GB-792.inc | 311 ---------------------
src/mainboard/google/rush/bct/sdram-unused.inc | 4 -
src/mainboard/google/rush/bct/spi.cfg | 31 --
src/mainboard/google/rush/board_info.txt | 6 -
src/mainboard/google/rush/boardid.c | 33 ---
src/mainboard/google/rush/bootblock.c | 99 -------
src/mainboard/google/rush/chromeos.c | 55 ----
src/mainboard/google/rush/chromeos.fmd | 27 --
src/mainboard/google/rush/devicetree.cb | 85 ------
src/mainboard/google/rush/ec_dummy.c | 22 --
src/mainboard/google/rush/mainboard.c | 199 -------------
src/mainboard/google/rush/memlayout.ld | 14 -
src/mainboard/google/rush/pmic.c | 108 -------
src/mainboard/google/rush/pmic.h | 44 ---
src/mainboard/google/rush/reset.c | 24 --
src/mainboard/google/rush/romstage.c | 64 -----
src/mainboard/google/rush/sdram_configs.c | 52 ----
src/mainboard/google/rush/verstage.c | 47 ----
29 files changed, 2388 deletions(-)
diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
deleted file mode 100644
index 09d9ebf..0000000
--- a/src/mainboard/google/rush/Kconfig
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_RUSH
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select SPI_FLASH
- select SOC_NVIDIA_TEGRA132
- select MAINBOARD_DO_SOR_INIT
- select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_4096
-
-config CHROMEOS
- select EC_SOFTWARE_SYNC
- select VBOOT_VBNV_EC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/rush
-
-config MAINBOARD_PART_NUMBER
- string
- default "Rush"
-
-config DRAM_SIZE_MB
- int
- default 2048
-
-choice
- prompt "BCT boot media"
- default RUSH_BCT_CFG_SPI
- help
- Which boot media to configure the BCT for.
-
-config RUSH_BCT_CFG_SPI
- bool "SPI"
- help
- Configure the BCT for booting from SPI.
-
-config RUSH_BCT_CFG_EMMC
- bool "eMMC"
- help
- Configure the BCT for booting from eMMC.
-
-endchoice
-
-config BOOT_MEDIA_SPI_BUS
- int "SPI bus with boot media ROM"
- range 1 6
- depends on RUSH_BCT_CFG_SPI
- default 4
- help
- Which SPI bus the boot media is connected to.
-
-config BOOT_MEDIA_SPI_CHIP_SELECT
- int "Chip select for SPI boot media"
- range 0 3
- depends on RUSH_BCT_CFG_SPI
- default 0
- help
- Which chip select to use for boot media.
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x2
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 1
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "RUSH TEST 9382"
-endif # BOARD_GOOGLE_RUSH
diff --git a/src/mainboard/google/rush/Kconfig.name b/src/mainboard/google/rush/Kconfig.name
deleted file mode 100644
index fff6eb4..0000000
--- a/src/mainboard/google/rush/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_RUSH
- bool "Rush"
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
deleted file mode 100644
index 1f1fa03..0000000
--- a/src/mainboard/google/rush/Makefile.inc
+++ /dev/null
@@ -1,47 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# Add a handler for BCT config files
-$(call add-special-class,bct-cfg)
-bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
-
-$(obj)/generated/bct.cfg:
- @printf " CAT $(subst $(obj)/,,$(@))\n"
- cat $^ > $@
-
-subdirs-y += bct
-
-bootblock-y += bootblock.c
-bootblock-y += pmic.c
-bootblock-y += reset.c
-
-verstage-y += verstage.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-bootblock-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
-verstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush/bct/Makefile.inc b/src/mainboard/google/rush/bct/Makefile.inc
deleted file mode 100644
index 1e90086..0000000
--- a/src/mainboard/google/rush/bct/Makefile.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2013 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bct-cfg-$(CONFIG_RUSH_BCT_CFG_EMMC) += emmc.cfg
-bct-cfg-$(CONFIG_RUSH_BCT_CFG_SPI) += spi.cfg
-bct-cfg-y += odmdata.cfg
-bct-cfg-y += jtag.cfg
-
-# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
-# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
-# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.
diff --git a/src/mainboard/google/rush/bct/cfg2inc.sh b/src/mainboard/google/rush/bct/cfg2inc.sh
deleted file mode 100755
index 0d03697..0000000
--- a/src/mainboard/google/rush/bct/cfg2inc.sh
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-#
-# This file is part of the coreboot project.
-#
-# Copyright 2014 Google Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-
-bct_cfg2inc() {
- local in_file="$1"
- local out_file="$2"
- echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
- # Note currently we can only handle DDR3 type memory, even in C
- # implementation.
- sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \
- "${in_file}" >> "${out_file}"
- echo "}," >>"${out_file}"
-}
-
-for file in $@; do
- echo "Generating $file => ${file%cfg}inc..."
- bct_cfg2inc "${file}" "${file%cfg}inc"
-done
diff --git a/src/mainboard/google/rush/bct/emmc.cfg b/src/mainboard/google/rush/bct/emmc.cfg
deleted file mode 100644
index 430ffd6..0000000
--- a/src/mainboard/google/rush/bct/emmc.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
-# Distributed under the terms of the GNU General Public License v2
-
-Version = 0x00130001;
-BlockSize = 0x00004000;
-PageSize = 0x00000200;
-PartitionSize = 0x01000000;
-
-DevType[0] = NvBootDevType_Sdmmc;
-DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
-DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
-DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
-DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;
diff --git a/src/mainboard/google/rush/bct/jtag.cfg b/src/mainboard/google/rush/bct/jtag.cfg
deleted file mode 100644
index f43e143..0000000
--- a/src/mainboard/google/rush/bct/jtag.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Set JtagCtrl to 1 to reenable Jtag
-#
-JtagCtrl = 0;
-#
-# Fill in chip unique id
-#
-# ChipUid can be found by running tegrarcm in tegra recovery mode
-# (also hooking up A-A USB cable) and looking for console output
-# on line starting with "Chip UID:"
-#
-# Command example:
-# $ sudo tegrarcm --bct=/build/nyan/firmware/bct/board.bct --bootloader=/build/nyan/firmware/u-boot.bin --loadaddr=0x80108000
-# Where board.bct and u-boot.bin do not have to be prebuilt.
-#
-ChipUid = 0x00000000000000000000000000000000;
diff --git a/src/mainboard/google/rush/bct/odmdata.cfg b/src/mainboard/google/rush/bct/odmdata.cfg
deleted file mode 100644
index d0ab2bf..0000000
--- a/src/mainboard/google/rush/bct/odmdata.cfg
+++ /dev/null
@@ -1 +0,0 @@
-OdmData = 0x80080000;
diff --git a/src/mainboard/google/rush/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/rush/bct/sdram-hynix-2GB-792.inc
deleted file mode 100644
index 60bf416..0000000
--- a/src/mainboard/google/rush/bct/sdram-hynix-2GB-792.inc
+++ /dev/null
@@ -1,311 +0,0 @@
-{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
- .MemoryType = NvBootMemoryType_Ddr3,
- .PllMInputDivider = 0x00000001,
- .PllMFeedbackDivider = 0x00000042,
- .PllMStableTime = 0x0000012c,
- .PllMSetupControl = 0x00000000,
- .PllMSelectDiv2 = 0x00000000,
- .PllMPDLshiftPh45 = 0x00000001,
- .PllMPDLshiftPh90 = 0x00000001,
- .PllMPDLshiftPh135 = 0x00000001,
- .PllMKCP = 0x00000000,
- .PllMKVCO = 0x00000000,
- .EmcBctSpare0 = 0x00000000,
- .EmcBctSpare1 = 0x00000000,
- .EmcBctSpare2 = 0x00000000,
- .EmcBctSpare3 = 0x00000000,
- .EmcBctSpare4 = 0x00000000,
- .EmcBctSpare5 = 0x00000000,
- .EmcBctSpare6 = 0x00000000,
- .EmcBctSpare7 = 0x00000000,
- .EmcBctSpare8 = 0x00000000,
- .EmcBctSpare9 = 0x00000000,
- .EmcBctSpare10 = 0x00000000,
- .EmcBctSpare11 = 0x00000000,
- .EmcClockSource = 0x80000000,
- .EmcAutoCalInterval = 0x001fffff,
- .EmcAutoCalConfig = 0xa1430000,
- .EmcAutoCalConfig2 = 0x00000000,
- .EmcAutoCalConfig3 = 0x00000000,
- .EmcAutoCalWait = 0x00000190,
- .EmcAdrCfg = 0x00000000,
- .EmcPinProgramWait = 0x00000001,
- .EmcPinExtraWait = 0x00000000,
- .EmcTimingControlWait = 0x00000000,
- .EmcRc = 0x00000025,
- .EmcRfc = 0x000000cd,
- .EmcRfcSlr = 0x00000000,
- .EmcRas = 0x00000019,
- .EmcRp = 0x0000000a,
- .EmcR2r = 0x00000000,
- .EmcW2w = 0x00000000,
- .EmcR2w = 0x00000007,
- .EmcW2r = 0x0000000d,
- .EmcR2p = 0x00000004,
- .EmcW2p = 0x00000013,
- .EmcRdRcd = 0x0000000a,
- .EmcWrRcd = 0x0000000a,
- .EmcRrd = 0x00000003,
- .EmcRext = 0x00000002,
- .EmcWext = 0x00000000,
- .EmcWdv = 0x00000006,
- .EmcWdvMask = 0x00000006,
- .EmcQUse = 0x0000000b,
- .EmcQuseWidth = 0x00000002,
- .EmcIbdly = 0x00000000,
- .EmcEInput = 0x00000003,
- .EmcEInputDuration = 0x0000000c,
- .EmcPutermExtra = 0x00090000,
- .EmcPutermWidth = 0x00000004,
- .EmcPutermAdj = 0x00000000,
- .EmcCdbCntl1 = 0x00000000,
- .EmcCdbCntl2 = 0x00000000,
- .EmcCdbCntl3 = 0x00000000,
- .EmcQRst = 0x00000002,
- .EmcQSafe = 0x00000011,
- .EmcRdv = 0x00000017,
- .EmcRdvMask = 0x00000019,
- .EmcQpop = 0x0000000f,
- .EmcCtt = 0x00000000,
- .EmcCttDuration = 0x00000004,
- .EmcRefresh = 0x000017eb,
- .EmcBurstRefreshNum = 0x00000000,
- .EmcPreRefreshReqCnt = 0x000005fa,
- .EmcPdEx2Wr = 0x00000003,
- .EmcPdEx2Rd = 0x00000003,
- .EmcPChg2Pden = 0x00000001,
- .EmcAct2Pden = 0x00000000,
- .EmcAr2Pden = 0x000000c7,
- .EmcRw2Pden = 0x00000018,
- .EmcTxsr = 0x000000d7,
- .EmcTxsrDll = 0x00000200,
- .EmcTcke = 0x00000005,
- .EmcTckesr = 0x00000006,
- .EmcTpd = 0x00000005,
- .EmcTfaw = 0x0000001d,
- .EmcTrpab = 0x00000000,
- .EmcTClkStable = 0x00000008,
- .EmcTClkStop = 0x00000008,
- .EmcTRefBw = 0x0000182c,
- .EmcFbioCfg5 = 0x104ab898,
- .EmcFbioCfg6 = 0x00000002,
- .EmcFbioSpare = 0x00000000,
- .EmcCfgRsv = 0xff00ff00,
- .EmcMrs = 0x80001d71,
- .EmcEmrs = 0x80100002,
- .EmcEmrs2 = 0x80200018,
- .EmcEmrs3 = 0x80300000,
- .EmcMrw1 = 0x00000000,
- .EmcMrw2 = 0x00000000,
- .EmcMrw3 = 0x00000000,
- .EmcMrw4 = 0x00000000,
- .EmcMrwExtra = 0x00000000,
- .EmcWarmBootMrwExtra = 0x00000000,
- .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
- .EmcExtraModeRegWriteEnable = 0x00000000,
- .EmcMrwResetCommand = 0x00000000,
- .EmcMrwResetNInitWait = 0x00000000,
- .EmcMrsWaitCnt = 0x00f7000e,
- .EmcMrsWaitCnt2 = 0x00f7000e,
- .EmcCfg = 0x73300000,
- .EmcCfg2 = 0x0000089d,
- .EmcCfgPipe = 0x000040a0,
- .EmcDbg = 0x01000c00,
- .EmcCmdQ = 0x10004408,
- .EmcMc2EmcQ = 0x06000404,
- .EmcDynSelfRefControl = 0x80003025,
- .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
- .EmcCfgDigDll = 0xe00701b1,
- .EmcCfgDigDllPeriod = 0x00008000,
- .EmcDevSelect = 0x00000002,
- .EmcSelDpdCtrl = 0x00040000,
- .EmcDllXformDqs0 = 0x00000008,
- .EmcDllXformDqs1 = 0x00000008,
- .EmcDllXformDqs2 = 0x00000008,
- .EmcDllXformDqs3 = 0x00000008,
- .EmcDllXformDqs4 = 0x00000008,
- .EmcDllXformDqs5 = 0x00000008,
- .EmcDllXformDqs6 = 0x00000008,
- .EmcDllXformDqs7 = 0x00000008,
- .EmcDllXformDqs8 = 0x00000008,
- .EmcDllXformDqs9 = 0x00000008,
- .EmcDllXformDqs10 = 0x00000008,
- .EmcDllXformDqs11 = 0x00000008,
- .EmcDllXformDqs12 = 0x00000008,
- .EmcDllXformDqs13 = 0x00000008,
- .EmcDllXformDqs14 = 0x00000008,
- .EmcDllXformDqs15 = 0x00000008,
- .EmcDllXformQUse0 = 0x00000000,
- .EmcDllXformQUse1 = 0x00000000,
- .EmcDllXformQUse2 = 0x00000000,
- .EmcDllXformQUse3 = 0x00000000,
- .EmcDllXformQUse4 = 0x00000000,
- .EmcDllXformQUse5 = 0x00000000,
- .EmcDllXformQUse6 = 0x00000000,
- .EmcDllXformQUse7 = 0x00000000,
- .EmcDllXformAddr0 = 0x0000000e,
- .EmcDllXformAddr1 = 0x0000000e,
- .EmcDllXformAddr2 = 0x00000000,
- .EmcDllXformAddr3 = 0x0000000e,
- .EmcDllXformAddr4 = 0x00000000,
- .EmcDllXformAddr5 = 0x00000000,
- .EmcDllXformQUse8 = 0x00000000,
- .EmcDllXformQUse9 = 0x00000000,
- .EmcDllXformQUse10 = 0x00000000,
- .EmcDllXformQUse11 = 0x00000000,
- .EmcDllXformQUse12 = 0x00000000,
- .EmcDllXformQUse13 = 0x00000000,
- .EmcDllXformQUse14 = 0x00000000,
- .EmcDllXformQUse15 = 0x00000000,
- .EmcDliTrimTxDqs0 = 0x00000000,
- .EmcDliTrimTxDqs1 = 0x00000000,
- .EmcDliTrimTxDqs2 = 0x00000000,
- .EmcDliTrimTxDqs3 = 0x00000000,
- .EmcDliTrimTxDqs4 = 0x00000000,
- .EmcDliTrimTxDqs5 = 0x00000000,
- .EmcDliTrimTxDqs6 = 0x00000000,
- .EmcDliTrimTxDqs7 = 0x00000000,
- .EmcDliTrimTxDqs8 = 0x00000000,
- .EmcDliTrimTxDqs9 = 0x00000000,
- .EmcDliTrimTxDqs10 = 0x00000000,
- .EmcDliTrimTxDqs11 = 0x00000000,
- .EmcDliTrimTxDqs12 = 0x00000000,
- .EmcDliTrimTxDqs13 = 0x00000000,
- .EmcDliTrimTxDqs14 = 0x00000000,
- .EmcDliTrimTxDqs15 = 0x00000000,
- .EmcDllXformDq0 = 0x0000000b,
- .EmcDllXformDq1 = 0x0000000b,
- .EmcDllXformDq2 = 0x0000000b,
- .EmcDllXformDq3 = 0x0000000b,
- .EmcDllXformDq4 = 0x0000000b,
- .EmcDllXformDq5 = 0x0000000b,
- .EmcDllXformDq6 = 0x0000000b,
- .EmcDllXformDq7 = 0x0000000b,
- .WarmBootWait = 0x00000002,
- .EmcCttTermCtrl = 0x00000802,
- .EmcOdtWrite = 0x00000000,
- .EmcOdtRead = 0x00000000,
- .EmcZcalInterval = 0x00020000,
- .EmcZcalWaitCnt = 0x00000042,
- .EmcZcalMrwCmd = 0x80000000,
- .EmcMrsResetDll = 0x00000000,
- .EmcZcalInitDev0 = 0x80000011,
- .EmcZcalInitDev1 = 0x00000000,
- .EmcZcalInitWait = 0x00000001,
- .EmcZcalWarmColdBootEnables = 0x00000003,
- .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
- .EmcZqCalDdr3WarmBoot = 0x00000000,
- .EmcZcalWarmBootWait = 0x00000001,
- .EmcMrsWarmBootEnable = 0x00000001,
- .EmcMrsResetDllWait = 0x00000000,
- .EmcMrsExtra = 0x80001d71,
- .EmcWarmBootMrsExtra = 0x80100002,
- .EmcEmrsDdr2DllEnable = 0x00000000,
- .EmcMrsDdr2DllReset = 0x00000000,
- .EmcEmrsDdr2OcdCalib = 0x00000000,
- .EmcDdr2Wait = 0x00000000,
- .EmcClkenOverride = 0x00000000,
- .McDisExtraSnapLevels = 0x00000000,
- .EmcExtraRefreshNum = 0x00000002,
- .EmcClkenOverrideAllWarmBoot = 0x00000000,
- .McClkenOverrideAllWarmBoot = 0x00000000,
- .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
- .PmcVddpSel = 0x00000002,
- .PmcVddpSelWait = 0x00000002,
- .PmcDdrPwr = 0x00000003,
- .PmcDdrCfg = 0x00002002,
- .PmcIoDpd3Req = 0x4fff2f97,
- .PmcIoDpd3ReqWait = 0x00000000,
- .PmcRegShort = 0x00000000,
- .PmcNoIoPower = 0x00000000,
- .PmcPorDpdCtrlWait = 0x00000000,
- .EmcXm2CmdPadCtrl = 0x100002a0,
- .EmcXm2CmdPadCtrl2 = 0x770c0000,
- .EmcXm2CmdPadCtrl3 = 0x050c0000,
- .EmcXm2CmdPadCtrl4 = 0x00000000,
- .EmcXm2CmdPadCtrl5 = 0x00111111,
- .EmcXm2DqsPadCtrl = 0x770c1414,
- .EmcXm2DqsPadCtrl2 = 0x0020013d,
- .EmcXm2DqsPadCtrl3 = 0x61861820,
- .EmcXm2DqsPadCtrl4 = 0x00514514,
- .EmcXm2DqsPadCtrl5 = 0x00514514,
- .EmcXm2DqsPadCtrl6 = 0x61861800,
- .EmcXm2DqPadCtrl = 0x770c2990,
- .EmcXm2DqPadCtrl2 = 0x00000000,
- .EmcXm2DqPadCtrl3 = 0x00000000,
- .EmcXm2ClkPadCtrl = 0x77ffc085,
- .EmcXm2ClkPadCtrl2 = 0x00000707,
- .EmcXm2CompPadCtrl = 0x81f1f108,
- .EmcXm2VttGenPadCtrl = 0x07070004,
- .EmcXm2VttGenPadCtrl2 = 0x00000000,
- .EmcXm2VttGenPadCtrl3 = 0x017fffff,
- .EmcAcpdControl = 0x00000000,
- .EmcSwizzleRank0ByteCfg = 0x00003120,
- .EmcSwizzleRank0Byte0 = 0x25143067,
- .EmcSwizzleRank0Byte1 = 0x45367102,
- .EmcSwizzleRank0Byte2 = 0x47106253,
- .EmcSwizzleRank0Byte3 = 0x04362175,
- .EmcSwizzleRank1ByteCfg = 0x00003120,
- .EmcSwizzleRank1Byte0 = 0x71546032,
- .EmcSwizzleRank1Byte1 = 0x35104276,
- .EmcSwizzleRank1Byte2 = 0x27043615,
- .EmcSwizzleRank1Byte3 = 0x72306145,
- .EmcDsrVttgenDrv = 0x0505003f,
- .EmcTxdsrvttgen = 0x00000000,
- .EmcBgbiasCtl0 = 0x00000000,
- .McEmemAdrCfg = 0x00000000,
- .McEmemAdrCfgDev0 = 0x00080303,
- .McEmemAdrCfgDev1 = 0x00080303,
- .McEmemAdrCfgBankMask0 = 0x00001248,
- .McEmemAdrCfgBankMask1 = 0x00002490,
- .McEmemAdrCfgBankMask2 = 0x00000920,
- .McEmemAdrCfgBankSwizzle3 = 0x00000001,
- .McEmemCfg = 0x00000800,
- .McEmemArbCfg = 0x0e00000b,
- .McEmemArbOutstandingReq = 0x80000040,
- .McEmemArbTimingRcd = 0x00000004,
- .McEmemArbTimingRp = 0x00000005,
- .McEmemArbTimingRc = 0x00000013,
- .McEmemArbTimingRas = 0x0000000c,
- .McEmemArbTimingFaw = 0x0000000f,
- .McEmemArbTimingRrd = 0x00000002,
- .McEmemArbTimingRap2Pre = 0x00000003,
- .McEmemArbTimingWap2Pre = 0x0000000c,
- .McEmemArbTimingR2R = 0x00000002,
- .McEmemArbTimingW2W = 0x00000002,
- .McEmemArbTimingR2W = 0x00000005,
- .McEmemArbTimingW2R = 0x00000008,
- .McEmemArbDaTurns = 0x08050202,
- .McEmemArbDaCovers = 0x00170e13,
- .McEmemArbMisc0 = 0x736c2414,
- .McEmemArbMisc1 = 0x70000f02,
- .McEmemArbRing1Throttle = 0x001f0000,
- .McEmemArbOverride = 0x10000000,
- .McEmemArbOverride1 = 0x00000000,
- .McEmemArbRsv = 0xff00ff00,
- .McClkenOverride = 0x00000000,
- .McStatControl = 0x00000000,
- .McDisplaySnapRing = 0x00000003,
- .McVideoProtectBom = 0xfff00000,
- .McVideoProtectBomAdrHi = 0x00000000,
- .McVideoProtectSizeMb = 0x00000000,
- .McVideoProtectVprOverride = 0xe4bac743,
- .McVideoProtectVprOverride1 = 0x00000013,
- .McVideoProtectGpuOverride0 = 0x00000000,
- .McVideoProtectGpuOverride1 = 0x00000000,
- .McSecCarveoutBom = 0xfff00000,
- .McSecCarveoutAdrHi = 0x00000000,
- .McSecCarveoutSizeMb = 0x00000000,
- .McVideoProtectWriteAccess = 0x00000000,
- .McSecCarveoutProtectWriteAccess = 0x00000000,
- .EmcCaTrainingEnable = 0x00000000,
- .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
- .EmcCaTrainingTimingCntl2 = 0x0000001f,
- .SwizzleRankByteEncode = 0x0000006f,
- .BootRomPatchControl = 0x00000000,
- .BootRomPatchData = 0x00000000,
- .McMtsCarveoutBom = 0xf8000000,
- .McMtsCarveoutAdrHi = 0x00000000,
- .McMtsCarveoutSizeMb = 0x00000080,
- .McMtsCarveoutRegCtrl = 0x00000001,
-},
diff --git a/src/mainboard/google/rush/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/rush/bct/sdram-hynix-2GB-924.inc
deleted file mode 100644
index 44d77cb..0000000
--- a/src/mainboard/google/rush/bct/sdram-hynix-2GB-924.inc
+++ /dev/null
@@ -1,311 +0,0 @@
-{ /* generated from sdram-hynix-2GB-924.cfg; do not edit. */
- .MemoryType = NvBootMemoryType_Ddr3,
- .PllMInputDivider = 0x00000001,
- .PllMFeedbackDivider = 0x0000004d,
- .PllMStableTime = 0x0000012c,
- .PllMSetupControl = 0x00000000,
- .PllMSelectDiv2 = 0x00000000,
- .PllMPDLshiftPh45 = 0x00000001,
- .PllMPDLshiftPh90 = 0x00000001,
- .PllMPDLshiftPh135 = 0x00000001,
- .PllMKCP = 0x00000000,
- .PllMKVCO = 0x00000000,
- .EmcBctSpare0 = 0x00000000,
- .EmcBctSpare1 = 0x00000000,
- .EmcBctSpare2 = 0x00000000,
- .EmcBctSpare3 = 0x00000000,
- .EmcBctSpare4 = 0x00000000,
- .EmcBctSpare5 = 0x00000000,
- .EmcBctSpare6 = 0x00000000,
- .EmcBctSpare7 = 0x00000000,
- .EmcBctSpare8 = 0x00000000,
- .EmcBctSpare9 = 0x00000000,
- .EmcBctSpare10 = 0x00000000,
- .EmcBctSpare11 = 0x00000000,
- .EmcClockSource = 0x80000000,
- .EmcAutoCalInterval = 0x001fffff,
- .EmcAutoCalConfig = 0xa1430101,
- .EmcAutoCalConfig2 = 0x00000000,
- .EmcAutoCalConfig3 = 0x00000000,
- .EmcAutoCalWait = 0x00000190,
- .EmcAdrCfg = 0x00000000,
- .EmcPinProgramWait = 0x00000001,
- .EmcPinExtraWait = 0x00000000,
- .EmcTimingControlWait = 0x00000000,
- .EmcRc = 0x0000002b,
- .EmcRfc = 0x000000f0,
- .EmcRfcSlr = 0x00000000,
- .EmcRas = 0x0000001e,
- .EmcRp = 0x0000000b,
- .EmcR2r = 0x00000000,
- .EmcW2w = 0x00000000,
- .EmcR2w = 0x0000000a,
- .EmcW2r = 0x0000000f,
- .EmcR2p = 0x00000005,
- .EmcW2p = 0x00000016,
- .EmcRdRcd = 0x0000000b,
- .EmcWrRcd = 0x0000000b,
- .EmcRrd = 0x00000004,
- .EmcRext = 0x00000002,
- .EmcWext = 0x00000000,
- .EmcWdv = 0x00000007,
- .EmcWdvMask = 0x00000007,
- .EmcQUse = 0x0000000d,
- .EmcQuseWidth = 0x00000002,
- .EmcIbdly = 0x00000000,
- .EmcEInput = 0x00000002,
- .EmcEInputDuration = 0x0000000f,
- .EmcPutermExtra = 0x000a0000,
- .EmcPutermWidth = 0x00000004,
- .EmcPutermAdj = 0x00000000,
- .EmcCdbCntl1 = 0x00000000,
- .EmcCdbCntl2 = 0x00000000,
- .EmcCdbCntl3 = 0x00000000,
- .EmcQRst = 0x00000001,
- .EmcQSafe = 0x00000016,
- .EmcRdv = 0x0000001a,
- .EmcRdvMask = 0x0000001c,
- .EmcQpop = 0x00000011,
- .EmcCtt = 0x00000000,
- .EmcCttDuration = 0x00000004,
- .EmcRefresh = 0x00001be7,
- .EmcBurstRefreshNum = 0x00000000,
- .EmcPreRefreshReqCnt = 0x000006f9,
- .EmcPdEx2Wr = 0x00000004,
- .EmcPdEx2Rd = 0x00000015,
- .EmcPChg2Pden = 0x00000001,
- .EmcAct2Pden = 0x00000000,
- .EmcAr2Pden = 0x000000e7,
- .EmcRw2Pden = 0x0000001b,
- .EmcTxsr = 0x000000fb,
- .EmcTxsrDll = 0x00000200,
- .EmcTcke = 0x00000006,
- .EmcTckesr = 0x00000007,
- .EmcTpd = 0x00000006,
- .EmcTfaw = 0x00000022,
- .EmcTrpab = 0x00000000,
- .EmcTClkStable = 0x0000000a,
- .EmcTClkStop = 0x0000000a,
- .EmcTRefBw = 0x00001c28,
- .EmcFbioCfg5 = 0x104ab898,
- .EmcFbioCfg6 = 0x00000000,
- .EmcFbioSpare = 0x00000000,
- .EmcCfgRsv = 0xff00ff00,
- .EmcMrs = 0x80000f15,
- .EmcEmrs = 0x80100002,
- .EmcEmrs2 = 0x80200020,
- .EmcEmrs3 = 0x80300000,
- .EmcMrw1 = 0x00000000,
- .EmcMrw2 = 0x00000000,
- .EmcMrw3 = 0x00000000,
- .EmcMrw4 = 0x00000000,
- .EmcMrwExtra = 0x00000000,
- .EmcWarmBootMrwExtra = 0x00000000,
- .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
- .EmcExtraModeRegWriteEnable = 0x00000000,
- .EmcMrwResetCommand = 0x00000000,
- .EmcMrwResetNInitWait = 0x00000000,
- .EmcMrsWaitCnt = 0x00cd000e,
- .EmcMrsWaitCnt2 = 0x00cd000e,
- .EmcCfg = 0x73300000,
- .EmcCfg2 = 0x0000089d,
- .EmcCfgPipe = 0x00004080,
- .EmcDbg = 0x01000c00,
- .EmcCmdQ = 0x10004408,
- .EmcMc2EmcQ = 0x06000404,
- .EmcDynSelfRefControl = 0x800037ea,
- .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
- .EmcCfgDigDll = 0xe00400b1,
- .EmcCfgDigDllPeriod = 0x00008000,
- .EmcDevSelect = 0x00000002,
- .EmcSelDpdCtrl = 0x00040000,
- .EmcDllXformDqs0 = 0x007fc005,
- .EmcDllXformDqs1 = 0x007fc005,
- .EmcDllXformDqs2 = 0x007f8008,
- .EmcDllXformDqs3 = 0x007f8008,
- .EmcDllXformDqs4 = 0x007fc005,
- .EmcDllXformDqs5 = 0x007f8008,
- .EmcDllXformDqs6 = 0x007fc005,
- .EmcDllXformDqs7 = 0x007fc005,
- .EmcDllXformDqs8 = 0x007fc005,
- .EmcDllXformDqs9 = 0x007fc005,
- .EmcDllXformDqs10 = 0x007f8008,
- .EmcDllXformDqs11 = 0x007f8008,
- .EmcDllXformDqs12 = 0x007fc005,
- .EmcDllXformDqs13 = 0x007f8008,
- .EmcDllXformDqs14 = 0x007fc005,
- .EmcDllXformDqs15 = 0x007fc005,
- .EmcDllXformQUse0 = 0x00000000,
- .EmcDllXformQUse1 = 0x00000000,
- .EmcDllXformQUse2 = 0x00000000,
- .EmcDllXformQUse3 = 0x00000000,
- .EmcDllXformQUse4 = 0x00000000,
- .EmcDllXformQUse5 = 0x00000000,
- .EmcDllXformQUse6 = 0x00000000,
- .EmcDllXformQUse7 = 0x00000000,
- .EmcDllXformAddr0 = 0x00018000,
- .EmcDllXformAddr1 = 0x00018000,
- .EmcDllXformAddr2 = 0x00000000,
- .EmcDllXformAddr3 = 0x00018000,
- .EmcDllXformAddr4 = 0x00018000,
- .EmcDllXformAddr5 = 0x00000000,
- .EmcDllXformQUse8 = 0x00000000,
- .EmcDllXformQUse9 = 0x00000000,
- .EmcDllXformQUse10 = 0x00000000,
- .EmcDllXformQUse11 = 0x00000000,
- .EmcDllXformQUse12 = 0x00000000,
- .EmcDllXformQUse13 = 0x00000000,
- .EmcDllXformQUse14 = 0x00000000,
- .EmcDllXformQUse15 = 0x00000000,
- .EmcDliTrimTxDqs0 = 0x00000000,
- .EmcDliTrimTxDqs1 = 0x00000000,
- .EmcDliTrimTxDqs2 = 0x00000000,
- .EmcDliTrimTxDqs3 = 0x00000000,
- .EmcDliTrimTxDqs4 = 0x00000000,
- .EmcDliTrimTxDqs5 = 0x00000000,
- .EmcDliTrimTxDqs6 = 0x00000000,
- .EmcDliTrimTxDqs7 = 0x00000000,
- .EmcDliTrimTxDqs8 = 0x00000000,
- .EmcDliTrimTxDqs9 = 0x00000000,
- .EmcDliTrimTxDqs10 = 0x00000000,
- .EmcDliTrimTxDqs11 = 0x00000000,
- .EmcDliTrimTxDqs12 = 0x00000000,
- .EmcDliTrimTxDqs13 = 0x00000000,
- .EmcDliTrimTxDqs14 = 0x00000000,
- .EmcDliTrimTxDqs15 = 0x00000000,
- .EmcDllXformDq0 = 0x00000007,
- .EmcDllXformDq1 = 0x00000007,
- .EmcDllXformDq2 = 0x00000007,
- .EmcDllXformDq3 = 0x00000007,
- .EmcDllXformDq4 = 0x00000007,
- .EmcDllXformDq5 = 0x00000007,
- .EmcDllXformDq6 = 0x00000007,
- .EmcDllXformDq7 = 0x00000007,
- .WarmBootWait = 0x00000002,
- .EmcCttTermCtrl = 0x00000802,
- .EmcOdtWrite = 0x00000000,
- .EmcOdtRead = 0x00000000,
- .EmcZcalInterval = 0x00020000,
- .EmcZcalWaitCnt = 0x0000004c,
- .EmcZcalMrwCmd = 0x80000000,
- .EmcMrsResetDll = 0x00000000,
- .EmcZcalInitDev0 = 0x80000011,
- .EmcZcalInitDev1 = 0x00000000,
- .EmcZcalInitWait = 0x00000001,
- .EmcZcalWarmColdBootEnables = 0x00000003,
- .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
- .EmcZqCalDdr3WarmBoot = 0x00000000,
- .EmcZcalWarmBootWait = 0x00000001,
- .EmcMrsWarmBootEnable = 0x00000001,
- .EmcMrsResetDllWait = 0x00000000,
- .EmcMrsExtra = 0x80000f15,
- .EmcWarmBootMrsExtra = 0x80100002,
- .EmcEmrsDdr2DllEnable = 0x00000000,
- .EmcMrsDdr2DllReset = 0x00000000,
- .EmcEmrsDdr2OcdCalib = 0x00000000,
- .EmcDdr2Wait = 0x00000000,
- .EmcClkenOverride = 0x00000000,
- .McDisExtraSnapLevels = 0x00000000,
- .EmcExtraRefreshNum = 0x00000002,
- .EmcClkenOverrideAllWarmBoot = 0x00000000,
- .McClkenOverrideAllWarmBoot = 0x00000000,
- .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
- .PmcVddpSel = 0x00000002,
- .PmcVddpSelWait = 0x00000002,
- .PmcDdrPwr = 0x00000003,
- .PmcDdrCfg = 0x00002002,
- .PmcIoDpd3Req = 0x4fff2f97,
- .PmcIoDpd3ReqWait = 0x00000000,
- .PmcRegShort = 0x00000000,
- .PmcNoIoPower = 0x00000000,
- .PmcPorDpdCtrlWait = 0x00000000,
- .EmcXm2CmdPadCtrl = 0x100002a0,
- .EmcXm2CmdPadCtrl2 = 0x770c0000,
- .EmcXm2CmdPadCtrl3 = 0x050c0000,
- .EmcXm2CmdPadCtrl4 = 0x00000000,
- .EmcXm2CmdPadCtrl5 = 0x00111111,
- .EmcXm2DqsPadCtrl = 0x770c1414,
- .EmcXm2DqsPadCtrl2 = 0x0120113d,
- .EmcXm2DqsPadCtrl3 = 0x5d569720,
- .EmcXm2DqsPadCtrl4 = 0x00492492,
- .EmcXm2DqsPadCtrl5 = 0x00552452,
- .EmcXm2DqsPadCtrl6 = 0x61751800,
- .EmcXm2DqPadCtrl = 0x770c2990,
- .EmcXm2DqPadCtrl2 = 0x00000000,
- .EmcXm2DqPadCtrl3 = 0x00000000,
- .EmcXm2ClkPadCtrl = 0x77ffc085,
- .EmcXm2ClkPadCtrl2 = 0x00000000,
- .EmcXm2CompPadCtrl = 0x81f1f108,
- .EmcXm2VttGenPadCtrl = 0x07070004,
- .EmcXm2VttGenPadCtrl2 = 0x00000000,
- .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
- .EmcAcpdControl = 0x00000000,
- .EmcSwizzleRank0ByteCfg = 0x00003120,
- .EmcSwizzleRank0Byte0 = 0x25143067,
- .EmcSwizzleRank0Byte1 = 0x45367102,
- .EmcSwizzleRank0Byte2 = 0x47106253,
- .EmcSwizzleRank0Byte3 = 0x04362175,
- .EmcSwizzleRank1ByteCfg = 0x00003120,
- .EmcSwizzleRank1Byte0 = 0x71546032,
- .EmcSwizzleRank1Byte1 = 0x35104276,
- .EmcSwizzleRank1Byte2 = 0x27043615,
- .EmcSwizzleRank1Byte3 = 0x72306145,
- .EmcDsrVttgenDrv = 0x0606003f,
- .EmcTxdsrvttgen = 0x00000000,
- .EmcBgbiasCtl0 = 0x00000000,
- .McEmemAdrCfg = 0x00000000,
- .McEmemAdrCfgDev0 = 0x00080303,
- .McEmemAdrCfgDev1 = 0x00080303,
- .McEmemAdrCfgBankMask0 = 0x00001248,
- .McEmemAdrCfgBankMask1 = 0x00002490,
- .McEmemAdrCfgBankMask2 = 0x00000920,
- .McEmemAdrCfgBankSwizzle3 = 0x00000001,
- .McEmemCfg = 0x00000800,
- .McEmemArbCfg = 0x0e00000d,
- .McEmemArbOutstandingReq = 0x80000040,
- .McEmemArbTimingRcd = 0x00000005,
- .McEmemArbTimingRp = 0x00000006,
- .McEmemArbTimingRc = 0x00000016,
- .McEmemArbTimingRas = 0x0000000e,
- .McEmemArbTimingFaw = 0x00000011,
- .McEmemArbTimingRrd = 0x00000002,
- .McEmemArbTimingRap2Pre = 0x00000004,
- .McEmemArbTimingWap2Pre = 0x0000000e,
- .McEmemArbTimingR2R = 0x00000002,
- .McEmemArbTimingW2W = 0x00000002,
- .McEmemArbTimingR2W = 0x00000007,
- .McEmemArbTimingW2R = 0x00000009,
- .McEmemArbDaTurns = 0x09070202,
- .McEmemArbDaCovers = 0x001a1016,
- .McEmemArbMisc0 = 0x734e2a17,
- .McEmemArbMisc1 = 0x70000f02,
- .McEmemArbRing1Throttle = 0x001f0000,
- .McEmemArbOverride = 0x10000000,
- .McEmemArbOverride1 = 0x00000000,
- .McEmemArbRsv = 0xff00ff00,
- .McClkenOverride = 0x00000000,
- .McStatControl = 0x00000000,
- .McDisplaySnapRing = 0x00000003,
- .McVideoProtectBom = 0xfff00000,
- .McVideoProtectBomAdrHi = 0x00000000,
- .McVideoProtectSizeMb = 0x00000000,
- .McVideoProtectVprOverride = 0xe4bac743,
- .McVideoProtectVprOverride1 = 0x00000013,
- .McVideoProtectGpuOverride0 = 0x00000000,
- .McVideoProtectGpuOverride1 = 0x00000000,
- .McSecCarveoutBom = 0xfff00000,
- .McSecCarveoutAdrHi = 0x00000000,
- .McSecCarveoutSizeMb = 0x00000000,
- .McVideoProtectWriteAccess = 0x00000000,
- .McSecCarveoutProtectWriteAccess = 0x00000000,
- .EmcCaTrainingEnable = 0x00000000,
- .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
- .EmcCaTrainingTimingCntl2 = 0x0000001f,
- .SwizzleRankByteEncode = 0x0000006f,
- .BootRomPatchControl = 0x00000000,
- .BootRomPatchData = 0x00000000,
- .McMtsCarveoutBom = 0xf8000000,
- .McMtsCarveoutAdrHi = 0x00000000,
- .McMtsCarveoutSizeMb = 0x00000080,
- .McMtsCarveoutRegCtrl = 0x00000001,
-},
diff --git a/src/mainboard/google/rush/bct/sdram-hynix-4GB-300.inc b/src/mainboard/google/rush/bct/sdram-hynix-4GB-300.inc
deleted file mode 100644
index 62b067f..0000000
--- a/src/mainboard/google/rush/bct/sdram-hynix-4GB-300.inc
+++ /dev/null
@@ -1,311 +0,0 @@
-{ /* generated from sdram-hynix-4GB-300.cfg, do not edit. */
- .MemoryType = NvBootMemoryType_Ddr3,
- .PllMInputDivider = 0x00000001,
- .PllMFeedbackDivider = 0x00000032,
- .PllMStableTime = 0x0000012c,
- .PllMSetupControl = 0x00000000,
- .PllMSelectDiv2 = 0x00000000,
- .PllMPDLshiftPh45 = 0x00000001,
- .PllMPDLshiftPh90 = 0x00000001,
- .PllMPDLshiftPh135 = 0x00000001,
- .PllMKCP = 0x00000000,
- .PllMKVCO = 0x00000000,
- .EmcBctSpare0 = 0x00000000,
- .EmcBctSpare1 = 0x00000000,
- .EmcBctSpare2 = 0x00000000,
- .EmcBctSpare3 = 0x00000000,
- .EmcBctSpare4 = 0x00000000,
- .EmcBctSpare5 = 0x00000000,
- .EmcBctSpare6 = 0x00000000,
- .EmcBctSpare7 = 0x00000000,
- .EmcBctSpare8 = 0x00000000,
- .EmcBctSpare9 = 0x00000000,
- .EmcBctSpare10 = 0x00000000,
- .EmcBctSpare11 = 0x00000000,
- .EmcClockSource = 0x00000002,
- .EmcAutoCalInterval = 0x001fffff,
- .EmcAutoCalConfig = 0xa1430f0f,
- .EmcAutoCalConfig2 = 0x00000000,
- .EmcAutoCalConfig3 = 0x00000000,
- .EmcAutoCalWait = 0x00000190,
- .EmcAdrCfg = 0x00000001,
- .EmcPinProgramWait = 0x00000001,
- .EmcPinExtraWait = 0x00000000,
- .EmcTimingControlWait = 0x00000000,
- .EmcRc = 0x0000000d,
- .EmcRfc = 0x00000067,
- .EmcRfcSlr = 0x00000000,
- .EmcRas = 0x00000009,
- .EmcRp = 0x00000003,
- .EmcR2r = 0x00000000,
- .EmcW2w = 0x00000000,
- .EmcR2w = 0x00000005,
- .EmcW2r = 0x00000008,
- .EmcR2p = 0x00000002,
- .EmcW2p = 0x00000009,
- .EmcRdRcd = 0x00000003,
- .EmcWrRcd = 0x00000003,
- .EmcRrd = 0x00000002,
- .EmcRext = 0x00000002,
- .EmcWext = 0x00000000,
- .EmcWdv = 0x00000003,
- .EmcWdvMask = 0x00000003,
- .EmcQUse = 0x00000005,
- .EmcQuseWidth = 0x00000002,
- .EmcIbdly = 0x00000000,
- .EmcEInput = 0x00000002,
- .EmcEInputDuration = 0x00000007,
- .EmcPutermExtra = 0x00020000,
- .EmcPutermWidth = 0x00000003,
- .EmcPutermAdj = 0x00000000,
- .EmcCdbCntl1 = 0x00000000,
- .EmcCdbCntl2 = 0x00000000,
- .EmcCdbCntl3 = 0x00000000,
- .EmcQRst = 0x00000001,
- .EmcQSafe = 0x0000000e,
- .EmcRdv = 0x00000010,
- .EmcRdvMask = 0x00000012,
- .EmcQpop = 0x00000009,
- .EmcCtt = 0x00000000,
- .EmcCttDuration = 0x00000003,
- .EmcRefresh = 0x000008e4,
- .EmcBurstRefreshNum = 0x00000000,
- .EmcPreRefreshReqCnt = 0x00000239,
- .EmcPdEx2Wr = 0x00000001,
- .EmcPdEx2Rd = 0x00000008,
- .EmcPChg2Pden = 0x00000001,
- .EmcAct2Pden = 0x00000000,
- .EmcAr2Pden = 0x00000065,
- .EmcRw2Pden = 0x0000000e,
- .EmcTxsr = 0x0000006c,
- .EmcTxsrDll = 0x00000200,
- .EmcTcke = 0x00000004,
- .EmcTckesr = 0x00000005,
- .EmcTpd = 0x00000004,
- .EmcTfaw = 0x00000009,
- .EmcTrpab = 0x00000000,
- .EmcTClkStable = 0x00000005,
- .EmcTClkStop = 0x00000005,
- .EmcTRefBw = 0x00000924,
- .EmcFbioCfg5 = 0x104ab098,
- .EmcFbioCfg6 = 0x00000000,
- .EmcFbioSpare = 0x00000000,
- .EmcCfgRsv = 0xff00ff00,
- .EmcMrs = 0x00000321,
- .EmcEmrs = 0x00100002,
- .EmcEmrs2 = 0x00200000,
- .EmcEmrs3 = 0x00300000,
- .EmcMrw1 = 0x00000000,
- .EmcMrw2 = 0x00000000,
- .EmcMrw3 = 0x00000000,
- .EmcMrw4 = 0x00000000,
- .EmcMrwExtra = 0x00000000,
- .EmcWarmBootMrwExtra = 0x00000000,
- .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
- .EmcExtraModeRegWriteEnable = 0x00000000,
- .EmcMrwResetCommand = 0x00000000,
- .EmcMrwResetNInitWait = 0x00000000,
- .EmcMrsWaitCnt = 0x0117000e,
- .EmcMrsWaitCnt2 = 0x0117000e,
- .EmcCfg = 0x73340000,
- .EmcCfg2 = 0x000008d5,
- .EmcCfgPipe = 0x000052a3,
- .EmcDbg = 0x01000c00,
- .EmcCmdQ = 0x10004408,
- .EmcMc2EmcQ = 0x06000404,
- .EmcDynSelfRefControl = 0x800012d7,
- .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
- .EmcCfgDigDll = 0x002c00a0,
- .EmcCfgDigDllPeriod = 0x00008000,
- .EmcDevSelect = 0x00000000,
- .EmcSelDpdCtrl = 0x00040128,
- .EmcDllXformDqs0 = 0x00030000,
- .EmcDllXformDqs1 = 0x00030000,
- .EmcDllXformDqs2 = 0x00030000,
- .EmcDllXformDqs3 = 0x00030000,
- .EmcDllXformDqs4 = 0x00030000,
- .EmcDllXformDqs5 = 0x00030000,
- .EmcDllXformDqs6 = 0x00030000,
- .EmcDllXformDqs7 = 0x00030000,
- .EmcDllXformDqs8 = 0x00030000,
- .EmcDllXformDqs9 = 0x00030000,
- .EmcDllXformDqs10 = 0x00030000,
- .EmcDllXformDqs11 = 0x00030000,
- .EmcDllXformDqs12 = 0x00030000,
- .EmcDllXformDqs13 = 0x00030000,
- .EmcDllXformDqs14 = 0x00030000,
- .EmcDllXformDqs15 = 0x00030000,
- .EmcDllXformQUse0 = 0x00000000,
- .EmcDllXformQUse1 = 0x00000000,
- .EmcDllXformQUse2 = 0x00000000,
- .EmcDllXformQUse3 = 0x00000000,
- .EmcDllXformQUse4 = 0x00000000,
- .EmcDllXformQUse5 = 0x00000000,
- .EmcDllXformQUse6 = 0x00000000,
- .EmcDllXformQUse7 = 0x00000000,
- .EmcDllXformAddr0 = 0x00084000,
- .EmcDllXformAddr1 = 0x00084000,
- .EmcDllXformAddr2 = 0x00010000,
- .EmcDllXformAddr3 = 0x00084000,
- .EmcDllXformAddr4 = 0x00084000,
- .EmcDllXformAddr5 = 0x00010000,
- .EmcDllXformQUse8 = 0x00000000,
- .EmcDllXformQUse9 = 0x00000000,
- .EmcDllXformQUse10 = 0x00000000,
- .EmcDllXformQUse11 = 0x00000000,
- .EmcDllXformQUse12 = 0x00000000,
- .EmcDllXformQUse13 = 0x00000000,
- .EmcDllXformQUse14 = 0x00000000,
- .EmcDllXformQUse15 = 0x00000000,
- .EmcDliTrimTxDqs0 = 0x00000000,
- .EmcDliTrimTxDqs1 = 0x00000000,
- .EmcDliTrimTxDqs2 = 0x00000000,
- .EmcDliTrimTxDqs3 = 0x00000000,
- .EmcDliTrimTxDqs4 = 0x00000000,
- .EmcDliTrimTxDqs5 = 0x00000000,
- .EmcDliTrimTxDqs6 = 0x00000000,
- .EmcDliTrimTxDqs7 = 0x00000000,
- .EmcDliTrimTxDqs8 = 0x00000000,
- .EmcDliTrimTxDqs9 = 0x00000000,
- .EmcDliTrimTxDqs10 = 0x00000000,
- .EmcDliTrimTxDqs11 = 0x00000000,
- .EmcDliTrimTxDqs12 = 0x00000000,
- .EmcDliTrimTxDqs13 = 0x00000000,
- .EmcDliTrimTxDqs14 = 0x00000000,
- .EmcDliTrimTxDqs15 = 0x00000000,
- .EmcDllXformDq0 = 0x00060000,
- .EmcDllXformDq1 = 0x00060000,
- .EmcDllXformDq2 = 0x00060000,
- .EmcDllXformDq3 = 0x00060000,
- .EmcDllXformDq4 = 0x00006000,
- .EmcDllXformDq5 = 0x00006000,
- .EmcDllXformDq6 = 0x00006000,
- .EmcDllXformDq7 = 0x00006000,
- .WarmBootWait = 0x00000002,
- .EmcCttTermCtrl = 0x00000802,
- .EmcOdtWrite = 0x00000000,
- .EmcOdtRead = 0x00000000,
- .EmcZcalInterval = 0x00020000,
- .EmcZcalWaitCnt = 0x00000042,
- .EmcZcalMrwCmd = 0x00000000,
- .EmcMrsResetDll = 0x00000000,
- .EmcZcalInitDev0 = 0x80000011,
- .EmcZcalInitDev1 = 0x40000011,
- .EmcZcalInitWait = 0x00000002,
- .EmcZcalWarmColdBootEnables = 0x00000003,
- .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
- .EmcZqCalDdr3WarmBoot = 0x00000000,
- .EmcZcalWarmBootWait = 0x00000002,
- .EmcMrsWarmBootEnable = 0x00000001,
- .EmcMrsResetDllWait = 0x00000000,
- .EmcMrsExtra = 0x00000321,
- .EmcWarmBootMrsExtra = 0x00100002,
- .EmcEmrsDdr2DllEnable = 0x00000000,
- .EmcMrsDdr2DllReset = 0x00000000,
- .EmcEmrsDdr2OcdCalib = 0x00000000,
- .EmcDdr2Wait = 0x00000000,
- .EmcClkenOverride = 0x00000000,
- .McDisExtraSnapLevels = 0x00000000,
- .EmcExtraRefreshNum = 0x00000002,
- .EmcClkenOverrideAllWarmBoot = 0x00000000,
- .McClkenOverrideAllWarmBoot = 0x00000000,
- .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
- .PmcVddpSel = 0x00000002,
- .PmcVddpSelWait = 0x00000002,
- .PmcDdrPwr = 0x00000003,
- .PmcDdrCfg = 0x00002002,
- .PmcIoDpd3Req = 0x4fffffff,
- .PmcIoDpd3ReqWait = 0x00000000,
- .PmcRegShort = 0x00000000,
- .PmcNoIoPower = 0x00000000,
- .PmcPorDpdCtrlWait = 0x00000000,
- .EmcXm2CmdPadCtrl = 0x10000280,
- .EmcXm2CmdPadCtrl2 = 0x770c0000,
- .EmcXm2CmdPadCtrl3 = 0x050c0000,
- .EmcXm2CmdPadCtrl4 = 0x00000000,
- .EmcXm2CmdPadCtrl5 = 0x00111111,
- .EmcXm2DqsPadCtrl = 0x770c1414,
- .EmcXm2DqsPadCtrl2 = 0x01231339,
- .EmcXm2DqsPadCtrl3 = 0x51451420,
- .EmcXm2DqsPadCtrl4 = 0x00514514,
- .EmcXm2DqsPadCtrl5 = 0x00514514,
- .EmcXm2DqsPadCtrl6 = 0x51451400,
- .EmcXm2DqPadCtrl = 0x770c2990,
- .EmcXm2DqPadCtrl2 = 0x00000000,
- .EmcXm2DqPadCtrl3 = 0x00000000,
- .EmcXm2ClkPadCtrl = 0x77ffc081,
- .EmcXm2ClkPadCtrl2 = 0x00000000,
- .EmcXm2CompPadCtrl = 0x81f1f108,
- .EmcXm2VttGenPadCtrl = 0x07070004,
- .EmcXm2VttGenPadCtrl2 = 0x00000000,
- .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
- .EmcAcpdControl = 0x00000000,
- .EmcSwizzleRank0ByteCfg = 0x00003120,
- .EmcSwizzleRank0Byte0 = 0x25143067,
- .EmcSwizzleRank0Byte1 = 0x45367102,
- .EmcSwizzleRank0Byte2 = 0x47106253,
- .EmcSwizzleRank0Byte3 = 0x04362175,
- .EmcSwizzleRank1ByteCfg = 0x00003120,
- .EmcSwizzleRank1Byte0 = 0x71546032,
- .EmcSwizzleRank1Byte1 = 0x35104276,
- .EmcSwizzleRank1Byte2 = 0x27043615,
- .EmcSwizzleRank1Byte3 = 0x72306145,
- .EmcDsrVttgenDrv = 0x0000003f,
- .EmcTxdsrvttgen = 0x00000096,
- .EmcBgbiasCtl0 = 0x00000000,
- .McEmemAdrCfg = 0x00000001,
- .McEmemAdrCfgDev0 = 0x00080303,
- .McEmemAdrCfgDev1 = 0x00080303,
- .McEmemAdrCfgBankMask0 = 0x00001248,
- .McEmemAdrCfgBankMask1 = 0x00002490,
- .McEmemAdrCfgBankMask2 = 0x00000920,
- .McEmemAdrCfgBankSwizzle3 = 0x00000001,
- .McEmemCfg = 0x00001000,
- .McEmemArbCfg = 0x08000004,
- .McEmemArbOutstandingReq = 0x80000040,
- .McEmemArbTimingRcd = 0x00000001,
- .McEmemArbTimingRp = 0x00000002,
- .McEmemArbTimingRc = 0x00000007,
- .McEmemArbTimingRas = 0x00000004,
- .McEmemArbTimingFaw = 0x00000005,
- .McEmemArbTimingRrd = 0x00000001,
- .McEmemArbTimingRap2Pre = 0x00000002,
- .McEmemArbTimingWap2Pre = 0x00000007,
- .McEmemArbTimingR2R = 0x00000002,
- .McEmemArbTimingW2W = 0x00000002,
- .McEmemArbTimingR2W = 0x00000004,
- .McEmemArbTimingW2R = 0x00000006,
- .McEmemArbDaTurns = 0x06040202,
- .McEmemArbDaCovers = 0x000b0607,
- .McEmemArbMisc0 = 0x77450e08,
- .McEmemArbMisc1 = 0x70000f03,
- .McEmemArbRing1Throttle = 0x001f0000,
- .McEmemArbOverride = 0x10000000,
- .McEmemArbOverride1 = 0x00000000,
- .McEmemArbRsv = 0xff00ff00,
- .McClkenOverride = 0x00000000,
- .McStatControl = 0x00000000,
- .McDisplaySnapRing = 0x00000003,
- .McVideoProtectBom = 0xfff00000,
- .McVideoProtectBomAdrHi = 0x00000000,
- .McVideoProtectSizeMb = 0x00000000,
- .McVideoProtectVprOverride = 0xe4bac743,
- .McVideoProtectVprOverride1 = 0x00000013,
- .McVideoProtectGpuOverride0 = 0x00000000,
- .McVideoProtectGpuOverride1 = 0x00000000,
- .McSecCarveoutBom = 0xfff00000,
- .McSecCarveoutAdrHi = 0x00000000,
- .McSecCarveoutSizeMb = 0x00000000,
- .McVideoProtectWriteAccess = 0x00000000,
- .McSecCarveoutProtectWriteAccess = 0x00000000,
- .EmcCaTrainingEnable = 0x00000000,
- .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
- .EmcCaTrainingTimingCntl2 = 0x0000001f,
- .SwizzleRankByteEncode = 0x0000006f,
- .BootRomPatchControl = 0x00000000,
- .BootRomPatchData = 0x00000000,
- .McMtsCarveoutBom = 0x78000000,
- .McMtsCarveoutAdrHi = 0x00000001,
- .McMtsCarveoutSizeMb = 0x00000080,
- .McMtsCarveoutRegCtrl = 0x00000001,
-},
diff --git a/src/mainboard/google/rush/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/rush/bct/sdram-hynix-4GB-792.inc
deleted file mode 100644
index 7e5f666..0000000
--- a/src/mainboard/google/rush/bct/sdram-hynix-4GB-792.inc
+++ /dev/null
@@ -1,311 +0,0 @@
-{ /* generated from sdram-hynix-4GB-792.cfg, do not edit. */
- .MemoryType = NvBootMemoryType_Ddr3,
- .PllMInputDivider = 0x00000001,
- .PllMFeedbackDivider = 0x00000042,
- .PllMStableTime = 0x0000012c,
- .PllMSetupControl = 0x00000000,
- .PllMSelectDiv2 = 0x00000000,
- .PllMPDLshiftPh45 = 0x00000001,
- .PllMPDLshiftPh90 = 0x00000001,
- .PllMPDLshiftPh135 = 0x00000001,
- .PllMKCP = 0x00000000,
- .PllMKVCO = 0x00000000,
- .EmcBctSpare0 = 0x00000000,
- .EmcBctSpare1 = 0x00000000,
- .EmcBctSpare2 = 0x00000000,
- .EmcBctSpare3 = 0x00000000,
- .EmcBctSpare4 = 0x00000000,
- .EmcBctSpare5 = 0x00000000,
- .EmcBctSpare6 = 0x00000000,
- .EmcBctSpare7 = 0x00000000,
- .EmcBctSpare8 = 0x00000000,
- .EmcBctSpare9 = 0x00000000,
- .EmcBctSpare10 = 0x00000000,
- .EmcBctSpare11 = 0x00000000,
- .EmcClockSource = 0x80000000,
- .EmcAutoCalInterval = 0x001fffff,
- .EmcAutoCalConfig = 0xa1430808,
- .EmcAutoCalConfig2 = 0x00000000,
- .EmcAutoCalConfig3 = 0x00000000,
- .EmcAutoCalWait = 0x00000190,
- .EmcAdrCfg = 0x00000001,
- .EmcPinProgramWait = 0x00000001,
- .EmcPinExtraWait = 0x00000000,
- .EmcTimingControlWait = 0x00000000,
- .EmcRc = 0x00000024,
- .EmcRfc = 0x00000114,
- .EmcRfcSlr = 0x00000000,
- .EmcRas = 0x00000019,
- .EmcRp = 0x0000000a,
- .EmcR2r = 0x00000000,
- .EmcW2w = 0x00000000,
- .EmcR2w = 0x00000008,
- .EmcW2r = 0x0000000d,
- .EmcR2p = 0x00000004,
- .EmcW2p = 0x00000013,
- .EmcRdRcd = 0x0000000a,
- .EmcWrRcd = 0x0000000a,
- .EmcRrd = 0x00000003,
- .EmcRext = 0x00000002,
- .EmcWext = 0x00000000,
- .EmcWdv = 0x00000006,
- .EmcWdvMask = 0x00000006,
- .EmcQUse = 0x0000000b,
- .EmcQuseWidth = 0x00000002,
- .EmcIbdly = 0x00000000,
- .EmcEInput = 0x00000002,
- .EmcEInputDuration = 0x0000000d,
- .EmcPutermExtra = 0x00080000,
- .EmcPutermWidth = 0x00000004,
- .EmcPutermAdj = 0x00000000,
- .EmcCdbCntl1 = 0x00000000,
- .EmcCdbCntl2 = 0x00000000,
- .EmcCdbCntl3 = 0x00000000,
- .EmcQRst = 0x00000001,
- .EmcQSafe = 0x00000014,
- .EmcRdv = 0x00000017,
- .EmcRdvMask = 0x00000019,
- .EmcQpop = 0x0000000f,
- .EmcCtt = 0x00000000,
- .EmcCttDuration = 0x00000004,
- .EmcRefresh = 0x000017e2,
- .EmcBurstRefreshNum = 0x00000000,
- .EmcPreRefreshReqCnt = 0x000005f8,
- .EmcPdEx2Wr = 0x00000003,
- .EmcPdEx2Rd = 0x00000011,
- .EmcPChg2Pden = 0x00000001,
- .EmcAct2Pden = 0x00000000,
- .EmcAr2Pden = 0x0000010d,
- .EmcRw2Pden = 0x00000018,
- .EmcTxsr = 0x0000011e,
- .EmcTxsrDll = 0x00000200,
- .EmcTcke = 0x00000005,
- .EmcTckesr = 0x00000006,
- .EmcTpd = 0x00000005,
- .EmcTfaw = 0x0000001d,
- .EmcTrpab = 0x00000000,
- .EmcTClkStable = 0x00000008,
- .EmcTClkStop = 0x00000008,
- .EmcTRefBw = 0x00001822,
- .EmcFbioCfg5 = 0x104ab098,
- .EmcFbioCfg6 = 0x00000000,
- .EmcFbioSpare = 0x00000000,
- .EmcCfgRsv = 0xff00ff00,
- .EmcMrs = 0x00000d71,
- .EmcEmrs = 0x00100002,
- .EmcEmrs2 = 0x00200018,
- .EmcEmrs3 = 0x00300000,
- .EmcMrw1 = 0x00000000,
- .EmcMrw2 = 0x00000000,
- .EmcMrw3 = 0x00000000,
- .EmcMrw4 = 0x00000000,
- .EmcMrwExtra = 0x00000000,
- .EmcWarmBootMrwExtra = 0x00000000,
- .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
- .EmcExtraModeRegWriteEnable = 0x00000000,
- .EmcMrwResetCommand = 0x00000000,
- .EmcMrwResetNInitWait = 0x00000000,
- .EmcMrsWaitCnt = 0x006f000e,
- .EmcMrsWaitCnt2 = 0x006f000e,
- .EmcCfg = 0x73300000,
- .EmcCfg2 = 0x0000089d,
- .EmcCfgPipe = 0x000040a0,
- .EmcDbg = 0x01000c00,
- .EmcCmdQ = 0x10004408,
- .EmcMc2EmcQ = 0x06000404,
- .EmcDynSelfRefControl = 0x80003012,
- .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
- .EmcCfgDigDll = 0xe00700b1,
- .EmcCfgDigDllPeriod = 0x00008000,
- .EmcDevSelect = 0x00000000,
- .EmcSelDpdCtrl = 0x00040000,
- .EmcDllXformDqs0 = 0x00000008,
- .EmcDllXformDqs1 = 0x00000008,
- .EmcDllXformDqs2 = 0x00000008,
- .EmcDllXformDqs3 = 0x00000008,
- .EmcDllXformDqs4 = 0x00000008,
- .EmcDllXformDqs5 = 0x00000008,
- .EmcDllXformDqs6 = 0x00000008,
- .EmcDllXformDqs7 = 0x00000008,
- .EmcDllXformDqs8 = 0x00000008,
- .EmcDllXformDqs9 = 0x00000008,
- .EmcDllXformDqs10 = 0x00000008,
- .EmcDllXformDqs11 = 0x00000008,
- .EmcDllXformDqs12 = 0x00000008,
- .EmcDllXformDqs13 = 0x00000008,
- .EmcDllXformDqs14 = 0x00000008,
- .EmcDllXformDqs15 = 0x00000008,
- .EmcDllXformQUse0 = 0x00000000,
- .EmcDllXformQUse1 = 0x00000000,
- .EmcDllXformQUse2 = 0x00000000,
- .EmcDllXformQUse3 = 0x00000000,
- .EmcDllXformQUse4 = 0x00000000,
- .EmcDllXformQUse5 = 0x00000000,
- .EmcDllXformQUse6 = 0x00000000,
- .EmcDllXformQUse7 = 0x00000000,
- .EmcDllXformAddr0 = 0x00038000,
- .EmcDllXformAddr1 = 0x00038000,
- .EmcDllXformAddr2 = 0x00000000,
- .EmcDllXformAddr3 = 0x00038000,
- .EmcDllXformAddr4 = 0x00038000,
- .EmcDllXformAddr5 = 0x00000000,
- .EmcDllXformQUse8 = 0x00000000,
- .EmcDllXformQUse9 = 0x00000000,
- .EmcDllXformQUse10 = 0x00000000,
- .EmcDllXformQUse11 = 0x00000000,
- .EmcDllXformQUse12 = 0x00000000,
- .EmcDllXformQUse13 = 0x00000000,
- .EmcDllXformQUse14 = 0x00000000,
- .EmcDllXformQUse15 = 0x00000000,
- .EmcDliTrimTxDqs0 = 0x00000005,
- .EmcDliTrimTxDqs1 = 0x00000005,
- .EmcDliTrimTxDqs2 = 0x00000003,
- .EmcDliTrimTxDqs3 = 0x00000005,
- .EmcDliTrimTxDqs4 = 0x00000005,
- .EmcDliTrimTxDqs5 = 0x00000002,
- .EmcDliTrimTxDqs6 = 0x00000005,
- .EmcDliTrimTxDqs7 = 0x00000005,
- .EmcDliTrimTxDqs8 = 0x00000005,
- .EmcDliTrimTxDqs9 = 0x00000005,
- .EmcDliTrimTxDqs10 = 0x00000003,
- .EmcDliTrimTxDqs11 = 0x00000005,
- .EmcDliTrimTxDqs12 = 0x00000005,
- .EmcDliTrimTxDqs13 = 0x00000002,
- .EmcDliTrimTxDqs14 = 0x00000005,
- .EmcDliTrimTxDqs15 = 0x00000005,
- .EmcDllXformDq0 = 0x00000009,
- .EmcDllXformDq1 = 0x0000000c,
- .EmcDllXformDq2 = 0x00000008,
- .EmcDllXformDq3 = 0x0000000a,
- .EmcDllXformDq4 = 0x0000000a,
- .EmcDllXformDq5 = 0x00000008,
- .EmcDllXformDq6 = 0x0000000a,
- .EmcDllXformDq7 = 0x00000008,
- .WarmBootWait = 0x00000002,
- .EmcCttTermCtrl = 0x00000802,
- .EmcOdtWrite = 0x00000000,
- .EmcOdtRead = 0x00000000,
- .EmcZcalInterval = 0x00020000,
- .EmcZcalWaitCnt = 0x00000042,
- .EmcZcalMrwCmd = 0x00000000,
- .EmcMrsResetDll = 0x00000000,
- .EmcZcalInitDev0 = 0x80000011,
- .EmcZcalInitDev1 = 0x40000011,
- .EmcZcalInitWait = 0x00000001,
- .EmcZcalWarmColdBootEnables = 0x00000003,
- .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
- .EmcZqCalDdr3WarmBoot = 0x00000000,
- .EmcZcalWarmBootWait = 0x00000001,
- .EmcMrsWarmBootEnable = 0x00000001,
- .EmcMrsResetDllWait = 0x00000000,
- .EmcMrsExtra = 0x00000d71,
- .EmcWarmBootMrsExtra = 0x00100002,
- .EmcEmrsDdr2DllEnable = 0x00000000,
- .EmcMrsDdr2DllReset = 0x00000000,
- .EmcEmrsDdr2OcdCalib = 0x00000000,
- .EmcDdr2Wait = 0x00000000,
- .EmcClkenOverride = 0x00000000,
- .McDisExtraSnapLevels = 0x00000000,
- .EmcExtraRefreshNum = 0x00000002,
- .EmcClkenOverrideAllWarmBoot = 0x00000000,
- .McClkenOverrideAllWarmBoot = 0x00000000,
- .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
- .PmcVddpSel = 0x00000002,
- .PmcVddpSelWait = 0x00000002,
- .PmcDdrPwr = 0x00000003,
- .PmcDdrCfg = 0x00002002,
- .PmcIoDpd3Req = 0x4fffffff,
- .PmcIoDpd3ReqWait = 0x00000000,
- .PmcRegShort = 0x00000000,
- .PmcNoIoPower = 0x00000000,
- .PmcPorDpdCtrlWait = 0x00000000,
- .EmcXm2CmdPadCtrl = 0x100002a0,
- .EmcXm2CmdPadCtrl2 = 0x770c0000,
- .EmcXm2CmdPadCtrl3 = 0x050c0000,
- .EmcXm2CmdPadCtrl4 = 0x00000000,
- .EmcXm2CmdPadCtrl5 = 0x00111111,
- .EmcXm2DqsPadCtrl = 0x770c1414,
- .EmcXm2DqsPadCtrl2 = 0x0120113d,
- .EmcXm2DqsPadCtrl3 = 0x61861820,
- .EmcXm2DqsPadCtrl4 = 0x00514514,
- .EmcXm2DqsPadCtrl5 = 0x00514514,
- .EmcXm2DqsPadCtrl6 = 0x61861800,
- .EmcXm2DqPadCtrl = 0x770c2990,
- .EmcXm2DqPadCtrl2 = 0x00000000,
- .EmcXm2DqPadCtrl3 = 0x00000000,
- .EmcXm2ClkPadCtrl = 0x77ffc085,
- .EmcXm2ClkPadCtrl2 = 0x00000000,
- .EmcXm2CompPadCtrl = 0x81f1f108,
- .EmcXm2VttGenPadCtrl = 0x07070004,
- .EmcXm2VttGenPadCtrl2 = 0x00000000,
- .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
- .EmcAcpdControl = 0x00000000,
- .EmcSwizzleRank0ByteCfg = 0x00003120,
- .EmcSwizzleRank0Byte0 = 0x25143067,
- .EmcSwizzleRank0Byte1 = 0x45367102,
- .EmcSwizzleRank0Byte2 = 0x47106253,
- .EmcSwizzleRank0Byte3 = 0x04362175,
- .EmcSwizzleRank1ByteCfg = 0x00003120,
- .EmcSwizzleRank1Byte0 = 0x71546032,
- .EmcSwizzleRank1Byte1 = 0x35104276,
- .EmcSwizzleRank1Byte2 = 0x27043615,
- .EmcSwizzleRank1Byte3 = 0x72306145,
- .EmcDsrVttgenDrv = 0x0606003f,
- .EmcTxdsrvttgen = 0x00000000,
- .EmcBgbiasCtl0 = 0x00000000,
- .McEmemAdrCfg = 0x00000001,
- .McEmemAdrCfgDev0 = 0x00080303,
- .McEmemAdrCfgDev1 = 0x00080303,
- .McEmemAdrCfgBankMask0 = 0x00001248,
- .McEmemAdrCfgBankMask1 = 0x00002490,
- .McEmemAdrCfgBankMask2 = 0x00000920,
- .McEmemAdrCfgBankSwizzle3 = 0x00000001,
- .McEmemCfg = 0x00001000,
- .McEmemArbCfg = 0x0e00000b,
- .McEmemArbOutstandingReq = 0x80000040,
- .McEmemArbTimingRcd = 0x00000004,
- .McEmemArbTimingRp = 0x00000005,
- .McEmemArbTimingRc = 0x00000013,
- .McEmemArbTimingRas = 0x0000000c,
- .McEmemArbTimingFaw = 0x0000000f,
- .McEmemArbTimingRrd = 0x00000002,
- .McEmemArbTimingRap2Pre = 0x00000003,
- .McEmemArbTimingWap2Pre = 0x0000000c,
- .McEmemArbTimingR2R = 0x00000002,
- .McEmemArbTimingW2W = 0x00000002,
- .McEmemArbTimingR2W = 0x00000006,
- .McEmemArbTimingW2R = 0x00000008,
- .McEmemArbDaTurns = 0x08060202,
- .McEmemArbDaCovers = 0x00170e13,
- .McEmemArbMisc0 = 0x746c2414,
- .McEmemArbMisc1 = 0x70000f02,
- .McEmemArbRing1Throttle = 0x001f0000,
- .McEmemArbOverride = 0x10000000,
- .McEmemArbOverride1 = 0x00000000,
- .McEmemArbRsv = 0xff00ff00,
- .McClkenOverride = 0x00000000,
- .McStatControl = 0x00000000,
- .McDisplaySnapRing = 0x00000003,
- .McVideoProtectBom = 0xfff00000,
- .McVideoProtectBomAdrHi = 0x00000000,
- .McVideoProtectSizeMb = 0x00000000,
- .McVideoProtectVprOverride = 0xe4bac743,
- .McVideoProtectVprOverride1 = 0x00000013,
- .McVideoProtectGpuOverride0 = 0x00000000,
- .McVideoProtectGpuOverride1 = 0x00000000,
- .McSecCarveoutBom = 0xfff00000,
- .McSecCarveoutAdrHi = 0x00000000,
- .McSecCarveoutSizeMb = 0x00000000,
- .McVideoProtectWriteAccess = 0x00000000,
- .McSecCarveoutProtectWriteAccess = 0x00000000,
- .EmcCaTrainingEnable = 0x00000000,
- .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
- .EmcCaTrainingTimingCntl2 = 0x0000001f,
- .SwizzleRankByteEncode = 0x0000006f,
- .BootRomPatchControl = 0x00000000,
- .BootRomPatchData = 0x00000000,
- .McMtsCarveoutBom = 0x78000000,
- .McMtsCarveoutAdrHi = 0x00000001,
- .McMtsCarveoutSizeMb = 0x00000080,
- .McMtsCarveoutRegCtrl = 0x00000001,
-},
diff --git a/src/mainboard/google/rush/bct/sdram-unused.inc b/src/mainboard/google/rush/bct/sdram-unused.inc
deleted file mode 100644
index bef63dc..0000000
--- a/src/mainboard/google/rush/bct/sdram-unused.inc
+++ /dev/null
@@ -1,4 +0,0 @@
-{ /* dummy. */
- .MemoryType = NvBootMemoryType_Unused,
- 0,
-},
diff --git a/src/mainboard/google/rush/bct/spi.cfg b/src/mainboard/google/rush/bct/spi.cfg
deleted file mode 100644
index a5ded0b..0000000
--- a/src/mainboard/google/rush/bct/spi.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
-# Distributed under the terms of the GNU General Public License v2
-
-Version = 0x00130001;
-BlockSize = 32768;
-PageSize = 2048;
-PartitionSize = 4194304;
-
-DevType[0] = NvBootDevType_Spi;
-DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
-DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
-DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
-DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
-
-DevType[1] = NvBootDevType_Spi;
-DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
-DeviceParam[1].SpiFlashParams.ClockDivider = 0x16;
-DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
-DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0;
-
-DevType[2] = NvBootDevType_Spi;
-DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
-DeviceParam[2].SpiFlashParams.ClockDivider = 0x16;
-DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
-DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0;
-
-DevType[3] = NvBootDevType_Spi;
-DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
-DeviceParam[3].SpiFlashParams.ClockDivider = 0x16;
-DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
-DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;
diff --git a/src/mainboard/google/rush/board_info.txt b/src/mainboard/google/rush/board_info.txt
deleted file mode 100644
index 7be004d..0000000
--- a/src/mainboard/google/rush/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Rush Nvidia Tegra132 reference board
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/rush/boardid.c b/src/mainboard/google/rush/boardid.c
deleted file mode 100644
index 7b28123..0000000
--- a/src/mainboard/google/rush/boardid.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
-
- if (id < 0) {
- id = gpio_get(GPIO(Q3)) << 0 |
- gpio_get(GPIO(T1)) << 1 |
- gpio_get(GPIO(X1)) << 2 |
- gpio_get(GPIO(X4)) << 3;
- printk(BIOS_SPEW, "Board ID: %#x.\n", id);
- }
-
- return id;
-}
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c
deleted file mode 100644
index 2786f72..0000000
--- a/src/mainboard/google/rush/bootblock.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <device/i2c.h>
-#include <soc/addressmap.h>
-#include <soc/clk_rst.h>
-#include <soc/clock.h>
-#include <soc/funitcfg.h>
-#include <soc/nvidia/tegra/i2c.h>
-#include <soc/padconfig.h>
-#include <soc/spi.h> /* FIXME: move back to soc code? */
-
-#include "pmic.h"
-
-static const struct pad_config uart_console_pads[] = {
- /* UARTA: tx and rx. */
- PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3),
- PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3),
- /*
- * Disable UART2 pads as they are default connected to UARTA controller.
- */
- PAD_CFG_UNUSED(UART2_RXD),
- PAD_CFG_UNUSED(UART2_TXD),
- PAD_CFG_UNUSED(UART2_RTS_N),
- PAD_CFG_UNUSED(UART2_CTS_N),
-};
-
-static const struct pad_config padcfgs[] = {
- /* Board ID bits 3:0 */
- PAD_CFG_GPIO_INPUT(GPIO_X4_AUD, PINMUX_PULL_NONE),
- PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE),
- PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE),
- PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
-
- /* Power Button */
- PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_NONE),
-
- /* Lid Open Switch */
- PAD_CFG_GPIO_INPUT(KB_ROW4, PINMUX_PULL_UP),
-};
-
-static const struct pad_config i2cpad[] = {
- /* PMIC i2C bus */
- PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
- PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
-};
-
-static const struct pad_config spipad[] = {
- /* SPI fLash: mosi, miso, clk, cs0 */
- PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
- PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
- PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4),
- PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
-};
-
-static const struct funit_cfg funitcfgs[] = {
- FUNIT_CFG(I2C5, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
- FUNIT_CFG(SBC4, PLLP, 33333, spipad, ARRAY_SIZE(spipad)),
-};
-
-void bootblock_mainboard_early_init(void)
-{
- soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
-}
-
-static void set_clock_sources(void)
-{
- /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
-}
-
-void bootblock_mainboard_init(void)
-{
- set_clock_sources();
-
- /* Set up the pads required to load romstage. */
- soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
- soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
-
- i2c_init(4);
- pmic_init(4);
-
- tegra_spi_init(4);
-}
diff --git a/src/mainboard/google/rush/chromeos.c b/src/mainboard/google/rush/chromeos.c
deleted file mode 100644
index 9ebc58d..0000000
--- a/src/mainboard/google/rush/chromeos.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"},
- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {GPIO(R4), ACTIVE_HIGH, -1, "lid"},
- {GPIO(Q0), ACTIVE_LOW, -1, "power"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {GPIO(I5), ACTIVE_LOW, -1, "reset"},
- };
-
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO(R1));
-}
diff --git a/src/mainboard/google/rush/chromeos.fmd b/src/mainboard/google/rush/chromeos.fmd
deleted file mode 100644
index 4326f24..0000000
--- a/src/mainboard/google/rush/chromeos.fmd
+++ /dev/null
@@ -1,27 +0,0 @@
-FLASH at 0x0 0x400000 {
- WP_RO at 0x0 0x300000 {
- RO_SECTION at 0x0 0x2f0000 {
- BOOTBLOCK at 0 128K
- COREBOOT(CBFS)@0x20000 0x1e0000
- FMAP at 0x200000 0x1000
- GBB at 0x201000 0xeef00
- RO_FRID at 0x2eff00 0x100
- }
- RO_VPD at 0x2f0000 0x10000
- }
- RW_SECTION_A at 0x300000 0x78000 {
- VBLOCK_A at 0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0x75f00
- RW_FWID_A at 0x77f00 0x100
- }
- RW_SHARED at 0x378000 0x4000 {
- SHARED_DATA at 0x0 0x4000
- }
- RW_ELOG at 0x37c000 0x4000
- RW_SECTION_B at 0x380000 0x78000 {
- VBLOCK_B at 0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0x75f00
- RW_FWID_B at 0x77f00 0x100
- }
- RW_VPD at 0x3f8000 0x8000
-}
diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb
deleted file mode 100644
index 6b3e148..0000000
--- a/src/mainboard/google/rush/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip soc/nvidia/tegra132
- device cpu_cluster 0 on
- end
-
- register "display_controller" = "TEGRA_ARM_DISPLAYA"
- register "xres" = "1366"
- register "yres" = "768"
-
- # framebuffer resolution
- register "display_xres" = "1368"
- register "display_yres" = "678"
-
- # bits per pixel and color depth
- register "framebuffer_bits_per_pixel" = "16"
- register "color_depth" = "6"
-
- register "panel_bits_per_pixel" = "18"
-
-# How to compute these: xrandr --verbose will give you this:
-#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
-# 2560 2608 2640 2720 hborder 0
-# 1700 1703 1713 1749 vborder 0
-#Then you can compute your values:
-#H front porch = 2608 - 2560 = 48
-#H sync = 2640 - 2608 = 32
-#H back porch = 2720 - 2640 = 80
-#V front porch = 1703 - 1700 = 3
-#V sync = 1713 - 1703 = 10
-#V back porch = 1749 - 1713 = 36
-#href_to_sync and vref_to_sync are from the vendor
-#this is just an example for a Pixel panel; other panels differ.
-# Here is a peppy panel:
-# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
-# h: width 1366 start 1502 end 1532 total 1592
-# v: height 768 start 776 end 788 total 800
- register "href_to_sync" = "1"
- register "hfront_porch" = "136"
- register "hsync_width" = "30"
- register "hback_porch" = "60"
-
- register "vref_to_sync" = "1"
- register "vfront_porch" = "8"
- register "vsync_width" = "12"
- register "vback_porch" = "12"
-
- register "pixel_clock" = "76400000"
-
- register "win_opt" = "SOR_ENABLE"
-
- #
- # dp specific fields
- #
- register "dp.pwm" = "1"
-
- # various panel delay time
- register "dp.vdd_to_hpd_delay_ms" = "200"
- register "dp.hpd_unplug_min_us" = "2000"
- register "dp.hpd_plug_min_us" = "250"
- register "dp.hpd_irq_min_us" = "250"
-
- # link configurations
- register "dp.lane_count" = "1"
- register "dp.enhanced_framing" = "1"
- register "dp.link_bw" = "10"
- # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
-
- register "dp.drive_current" = "0x40404040"
- register "dp.preemphasis" = "0x0f0f0f0f"
- register "dp.postcursor" = "0"
-end
diff --git a/src/mainboard/google/rush/ec_dummy.c b/src/mainboard/google/rush/ec_dummy.c
deleted file mode 100644
index d720984..0000000
--- a/src/mainboard/google/rush/ec_dummy.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Dummy CHROMEEC file to provide stub functions for vboot compilation */
-
-#include <stdint.h>
-
-int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len);
-int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
-{
- return 0;
-}
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
deleted file mode 100644
index 4a8f936..0000000
--- a/src/mainboard/google/rush/mainboard.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/mmu.h>
-#include <bootmode.h>
-#include <boot/coreboot_tables.h>
-#include <delay.h>
-#include <device/device.h>
-#include <memrange.h>
-#include <soc/addressmap.h>
-#include <soc/clk_rst.h>
-#include <soc/clock.h>
-#include <soc/funitcfg.h>
-#include <soc/nvidia/tegra/i2c.h>
-#include <soc/nvidia/tegra/usb.h>
-#include <soc/padconfig.h>
-#include <soc/spi.h>
-#include <soc/nvidia/tegra/dc.h>
-#include <soc/display.h>
-
-static const struct pad_config sdmmc3_pad[] = {
- /* MMC3(SDCARD) */
- PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_DAT0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_DAT1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_DAT2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_DAT3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_CLK_LB_IN, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
- PAD_CFG_SFIO(SDMMC3_CLK_LB_OUT, PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN, SDMMC3),
- /* MMC3 Card Detect pin */
- PAD_CFG_GPIO_INPUT(SDMMC3_CD_N, PINMUX_PULL_UP),
- /* Disable SD card reader power so it can be reset even on warm boot.
- Payloads must enable power before accessing SD card slots. */
- PAD_CFG_GPIO_OUT0(KB_ROW0, PINMUX_PULL_NONE),
-};
-
-static const struct pad_config sdmmc4_pad[] = {
- /* MMC4 (eMMC) */
- PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT4, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT5, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
- PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
-};
-
-static const struct pad_config padcfgs[] = {
- /* We pull the USB VBUS signals up but keep them as inputs since the
- * voltage source likes to drive them low on overcurrent conditions */
- PAD_CFG_GPIO_INPUT(USB_VBUS_EN0, PINMUX_PULL_UP),
- PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_UP),
-
- /* backlight_vdd_gpio: P2 */
- PAD_CFG_GPIO_OUT0(DAP3_DOUT, PINMUX_PULL_NONE),
-
- /* backlight_en_gpio: H2 */
- PAD_CFG_GPIO_OUT0(GPIO_PH2, PINMUX_PULL_NONE),
-
- /* backlight_pwm: H1 */
- PAD_CFG_SFIO(GPIO_PH1, PINMUX_PULL_NONE, PWM1),
-
- /* DP HPD */
- PAD_CFG_SFIO(DP_HPD, PINMUX_INPUT_ENABLE, DP),
-};
-
-static const struct pad_config i2c1_pad[] = {
- /* GEN1 I2C */
- PAD_CFG_SFIO(GEN1_I2C_SCL, PINMUX_INPUT_ENABLE, I2C1),
- PAD_CFG_SFIO(GEN1_I2C_SDA, PINMUX_INPUT_ENABLE, I2C1),
-};
-
-static const struct funit_cfg funitcfgs[] = {
- FUNIT_CFG(SDMMC3, PLLP, 48000, sdmmc3_pad, ARRAY_SIZE(sdmmc3_pad)),
- FUNIT_CFG(SDMMC4, PLLP, 48000, sdmmc4_pad, ARRAY_SIZE(sdmmc4_pad)),
- FUNIT_CFG(I2C1, PLLP, 100, i2c1_pad, ARRAY_SIZE(i2c1_pad)),
-};
-
-static void setup_ec_spi(void)
-{
- struct tegra_spi_channel *spi;
-
- spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
-}
-
-static void setup_usb(void)
-{
- clock_enable_clear_reset(CLK_L_USBD, CLK_H_USB3, 0, 0, 0, 0);
-
- usb_setup_utmip((void *)TEGRA_USBD_BASE);
- usb_setup_utmip((void *)TEGRA_USB3_BASE);
-}
-
-static const struct pad_config i2s1_pad[] = {
- /* I2S1 */
- PAD_CFG_SFIO(DAP2_SCLK, PINMUX_INPUT_ENABLE, I2S1),
- PAD_CFG_SFIO(DAP2_FS, PINMUX_INPUT_ENABLE, I2S1),
- PAD_CFG_SFIO(DAP2_DOUT, PINMUX_INPUT_ENABLE, I2S1),
- PAD_CFG_SFIO(DAP2_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1),
- /* codec MCLK via EXTPERIPH1 */
- PAD_CFG_SFIO(DAP_MCLK1, PINMUX_PULL_NONE, EXTPERIPH1),
-};
-
-static const struct funit_cfg audio_funit[] = {
- /* We need 1.5MHz for I2S1. So we use CLK_M */
- FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)),
-};
-
-static void configure_display_clocks(void)
-{
- u32 lclks = CLK_L_DISP1 | CLK_L_HOST1X | CLK_L_PWM;
- u32 xclks = CLK_X_DPAUX | CLK_X_SOR0;
-
- clock_enable_clear_reset(lclks, 0, 0, 0, 0, xclks);
-
- /* Give clocks time to stabilize. */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-static int configure_display_blocks(void)
-{
- soc_configure_host1x();
-
- /* enable display related clocks */
- configure_display_clocks();
-
- return 0;
-}
-
-/* Audio init: clocks and enables/resets */
-static void setup_audio(void)
-{
- /*
- * External peripheral 1: audio codec (max98090) uses 12MHz CLK1
- * NOTE: We can't use a funits struct/call here because EXTPERIPH1/2/3
- * don't have BASE regs or CAR RST/ENA bits. Also, the mux setting for
- * EXTPERIPH1/DAP_MCLK1 is rolled into the I2S1 padcfg.
- */
- clock_configure_source(extperiph1, CLK_M, 12000);
-
- soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
-
- clock_external_output(1); /* For external MAX98090 audio codec. */
-
- /*
- * Confirmed by NVIDIA hardware team, we need to take ALL audio devices
- * connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
- * of reset and clock-enabled, otherwise reading AHUB devices (in our
- * case, I2S/APBIF/AUDIO<XBAR>) will hang.
- */
- clock_enable_audio();
-}
-
-static void mainboard_init(device_t dev)
-{
- soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
- soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
-
- setup_ec_spi();
- setup_usb();
-
- setup_audio();
- i2c_init(I2C1_BUS); /* for max98090 codec */
-
- /* if panel needs to bringup */
- if (display_init_required())
- configure_display_blocks();
-}
-
-void display_startup(device_t dev)
-{
- dp_display_startup(dev);
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .name = "rush",
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
deleted file mode 100644
index 2c33306..0000000
--- a/src/mainboard/google/rush/memlayout.ld
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/rush/pmic.c b/src/mainboard/google/rush/pmic.c
deleted file mode 100644
index a2769ee..0000000
--- a/src/mainboard/google/rush/pmic.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/i2c.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "pmic.h"
-#include "reset.h"
-
-enum {
- AS3722_I2C_ADDR = 0x40
-};
-
-struct as3722_init_reg {
- u8 reg;
- u8 val;
- u8 delay;
-};
-
-static struct as3722_init_reg init_list[] = {
- {AS3722_SDO0, 0x3C, 1},
- {AS3722_SDO1, 0x32, 0},
- {AS3722_LDO3, 0x59, 0},
- {AS3722_SDO2, 0x3C, 0},
- {AS3722_SDO3, 0x00, 0},
- {AS3722_SDO4, 0x00, 0},
- {AS3722_SDO5, 0x50, 0},
- {AS3722_SDO6, 0x28, 1},
- {AS3722_LDO0, 0x8A, 0},
- {AS3722_LDO1, 0x00, 0},
- {AS3722_LDO2, 0x10, 0},
- {AS3722_LDO4, 0x00, 0},
- {AS3722_LDO5, 0x00, 0},
- {AS3722_LDO6, 0x00, 0},
- {AS3722_LDO7, 0x00, 0},
- {AS3722_LDO9, 0x00, 0},
- {AS3722_LDO10, 0x00, 0},
- {AS3722_LDO11, 0x00, 1},
-};
-
-static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
-{
- if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
- printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
- __func__, reg, val);
- /* Reset the SoC on any PMIC write error */
- cpu_reset();
- } else {
- if (do_delay)
- udelay(500);
- }
-}
-
-static void pmic_slam_defaults(unsigned bus)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(init_list); i++) {
- struct as3722_init_reg *reg = &init_list[i];
- pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
- }
-}
-
-void pmic_init(unsigned bus)
-{
- /*
- * Don't need to set up VDD_CORE - already done - by OTP
- * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
- * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
- */
-
- /* Restore PMIC POR defaults, in case kernel changed 'em */
- pmic_slam_defaults(bus);
-
- /* SDO0: Set VDD_CPU to 1.2V. */
- pmic_write_reg(bus, 0x00, 0x50, 1);
-
- /* SDO6: Set VDD_GPU to 1.0V. */
- pmic_write_reg(bus, 0x06, 0x28, 1);
-
- /* LDO2: Set +1.2V_GEN_AVDD to 1.2V */
- pmic_write_reg(bus, 0x12, 0x10, 1);
-
- /*
- * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
- * the value (register 0x20 bit 4)
- */
- pmic_write_reg(bus, 0x0c, 0x07, 0);
- pmic_write_reg(bus, 0x20, 0x10, 1);
-
- printk(BIOS_DEBUG, "PMIC init done\n");
-}
diff --git a/src/mainboard/google/rush/pmic.h b/src/mainboard/google/rush/pmic.h
deleted file mode 100644
index bae2db9..0000000
--- a/src/mainboard/google/rush/pmic.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__
-#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__
-
-enum {
- AS3722_SDO0 = 0,
- AS3722_SDO1,
- AS3722_SDO2,
- AS3722_SDO3,
- AS3722_SDO4,
- AS3722_SDO5,
- AS3722_SDO6,
-
- AS3722_LDO0 = 0x10,
- AS3722_LDO1,
- AS3722_LDO2,
- AS3722_LDO3,
- AS3722_LDO4,
- AS3722_LDO5,
- AS3722_LDO6,
- AS3722_LDO7,
-
- AS3722_LDO9 = 0x19,
- AS3722_LDO10,
- AS3722_LDO11,
-};
-
-void pmic_init(unsigned bus);
-
-#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */
diff --git a/src/mainboard/google/rush/reset.c b/src/mainboard/google/rush/reset.c
deleted file mode 100644
index 4cc9a1e..0000000
--- a/src/mainboard/google/rush/reset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-void hard_reset(void)
-{
- gpio_output(GPIO(I5), 0);
- while(1);
-}
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
deleted file mode 100644
index 0bf2173..0000000
--- a/src/mainboard/google/rush/romstage.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/addressmap.h>
-#include <soc/clock.h>
-#include <soc/funitcfg.h>
-#include <soc/nvidia/tegra/i2c.h>
-#include <soc/padconfig.h>
-#include <soc/romstage.h>
-
-static const struct pad_config padcfgs[] = {
- /* SOC_WARM_RESET_L */
- PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
-};
-
-static const struct pad_config i2cpad[] = {
- /* TPM I2C */
- PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
- PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
-};
-
-static const struct pad_config spipad[] = {
- /* EC on SPI1: mosi, miso, clk, cs */
- PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
- PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
- PAD_CFG_SFIO(ULPI_NXT, PINMUX_INPUT_ENABLE, SPI1),
- PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
-};
-
-static const struct funit_cfg funitcfgs[] = {
- FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
- FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
-};
-
-void romstage_mainboard_init(void)
-{
- /* Bring up controller interfaces for ramstage loading. */
- soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
- soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
-
- /* TPM I2C bus */
- i2c_init(2);
-}
-
-void mainboard_configure_pmc(void)
-{
-}
-
-void mainboard_enable_vdd_cpu(void)
-{
- /* VDD_CPU is already enabled in bootblock. */
-}
diff --git a/src/mainboard/google/rush/sdram_configs.c b/src/mainboard/google/rush/sdram_configs.c
deleted file mode 100644
index ab1744a..0000000
--- a/src/mainboard/google/rush/sdram_configs.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <soc/sdram_configs.h>
-
-static struct sdram_params sdram_configs[] = {
-#include "bct/sdram-hynix-2GB-924.inc" /* ram_code = 0000 */
-#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 0001 */
-#include "bct/sdram-unused.inc" /* ram_code = 0010 */
-#include "bct/sdram-unused.inc" /* ram_code = 0011 */
-#include "bct/sdram-unused.inc" /* ram_code = 0100 */
-#include "bct/sdram-unused.inc" /* ram_code = 0101 */
-#include "bct/sdram-unused.inc" /* ram_code = 0110 */
-#include "bct/sdram-unused.inc" /* ram_code = 0111 */
-#include "bct/sdram-unused.inc" /* ram_code = 1000 */
-#include "bct/sdram-unused.inc" /* ram_code = 1001 */
-#include "bct/sdram-unused.inc" /* ram_code = 1010 */
-#include "bct/sdram-unused.inc" /* ram_code = 1011 */
-#include "bct/sdram-unused.inc" /* ram_code = 1100 */
-#include "bct/sdram-unused.inc" /* ram_code = 1101 */
-#include "bct/sdram-unused.inc" /* ram_code = 1110 */
-#include "bct/sdram-unused.inc" /* ram_code = 1111 */
-};
-
-const struct sdram_params *get_sdram_config()
-{
- uint32_t ramcode = sdram_get_ram_code();
- /*
- * If we need to apply some special hacks to RAMCODE mapping (ex, by
- * board_id), do that now.
- */
-
- printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
- if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
- sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused)
- die("Invalid RAMCODE.");
-
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/rush/verstage.c b/src/mainboard/google/rush/verstage.c
deleted file mode 100644
index b922d2f..0000000
--- a/src/mainboard/google/rush/verstage.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/addressmap.h>
-#include <soc/funitcfg.h>
-#include <soc/padconfig.h>
-#include <soc/verstage.h>
-#include <soc/nvidia/tegra/i2c.h>
-
-static const struct pad_config i2cpad[] = {
- /* TPM I2C */
- PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
- PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
-};
-
-static const struct pad_config spipad[] = {
- /* EC on SPI1: mosi, miso, clk, cs */
- PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
- PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
- PAD_CFG_SFIO(ULPI_NXT, PINMUX_INPUT_ENABLE, SPI1),
- PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
-};
-
-static const struct funit_cfg funitcfgs[] = {
- FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
- FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
-};
-
-void verstage_mainboard_init(void)
-{
- soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
-
- /* TPM I2C bus */
- i2c_init(2);
-}
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