[coreboot-gerrit] Patch set updated for coreboot: src/southbridge: space required before the open parenthesis '('
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Aug 22 13:01:08 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16290
-gerrit
commit 7baa69ed3b875c8931e57dd7c08b49b0854f2073
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Aug 21 18:36:06 2016 +0200
src/southbridge: space required before the open parenthesis '('
Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/amd/amd8132/bridge.c | 2 +-
src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++---
src/southbridge/broadcom/bcm5785/early_setup.c | 6 +++---
src/southbridge/intel/bd82x6x/smihandler.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/sata.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +-
src/southbridge/intel/fsp_i89xx/sata.c | 2 +-
src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +-
src/southbridge/intel/fsp_rangeley/sata.c | 2 +-
src/southbridge/intel/i3100/lpc.c | 6 +++---
src/southbridge/intel/i82801dx/smihandler.c | 2 +-
src/southbridge/intel/i82801ex/i82801ex.c | 4 ++--
src/southbridge/intel/i82801gx/sata.c | 2 +-
src/southbridge/intel/i82801gx/smihandler.c | 2 +-
src/southbridge/intel/i82801ix/smihandler.c | 2 +-
src/southbridge/intel/ibexpeak/smihandler.c | 2 +-
src/southbridge/intel/lynxpoint/sata.c | 2 +-
src/southbridge/sis/sis966/aza.c | 8 ++++----
src/southbridge/sis/sis966/ide.c | 4 ++--
src/southbridge/sis/sis966/lpc.c | 2 +-
src/southbridge/sis/sis966/nic.c | 26 +++++++++++++-------------
src/southbridge/sis/sis966/sata.c | 4 ++--
src/southbridge/sis/sis966/usb.c | 4 ++--
src/southbridge/sis/sis966/usb2.c | 8 ++++----
24 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index ee45c65..4df33da 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -386,7 +386,7 @@ static void amd8132_ioapic_init(device_t dev)
}
- if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+ if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
//for b1 b2
/* Errata #73 */
dword = pci_read_config32(dev, 0x80);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 7e8d8c3..efe38ab 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -46,10 +46,10 @@ void bcm5785_enable(device_t dev)
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
- if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
- if(dev->device == 0x0036) //PCI-X Bridge
+ if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+ if (dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
- else if(dev->device == 0x0223) // USB
+ else if (dev->device == 0x0223) // USB
{ devfn -= (1<<3); }
}
sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn);
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index e29fab4..3ddc9ca 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -47,13 +47,13 @@ static void bcm5785_enable_wdt_port_cf9(void)
dword_old = pci_read_config32(dev, 0x4c);
dword = dword_old | (1<<4); //enable Timer Func
- if(dword != dword_old ) {
+ if (dword != dword_old ) {
pci_write_config32(dev, 0x4c, dword);
}
dword_old = pci_read_config32(dev, 0x6c);
dword = dword_old | (1<<9); //unhide Timer Func in pci space
- if(dword != dword_old ) {
+ if (dword != dword_old ) {
pci_write_config32(dev, 0x6c, dword);
}
@@ -149,7 +149,7 @@ static void bcm5785_enable_msg(void)
// bit 1: enable upsteam messages
// bit 0: enable shutdowm message to init generation
dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
- if(dword != dword_old ) {
+ if (dword != dword_old ) {
pci_write_config32(dev, 0x6c, dword);
}
}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index e4e5b81..bc19b78 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c
index 81a5d7d..6130646 100644
--- a/src/southbridge/intel/fsp_bd82x6x/sata.c
+++ b/src/southbridge/intel/fsp_bd82x6x/sata.c
@@ -52,7 +52,7 @@ static void sata_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 987d6d1..77ada10 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c
index 87d5431..810847a 100644
--- a/src/southbridge/intel/fsp_i89xx/sata.c
+++ b/src/southbridge/intel/fsp_i89xx/sata.c
@@ -52,7 +52,7 @@ static void sata_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index e0d19d6..27b8166 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index 4861f83..624af23 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -60,7 +60,7 @@ static void sata_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set the controller mode */
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 4d529ca..77853a8 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -200,13 +200,13 @@ static void i3100_pirq_init(device_t dev)
/* Get the chip configuration */
config = dev->chip_info;
- if(config->pirq_a_d)
+ if (config->pirq_a_d)
pci_write_config32(dev, 0x60, config->pirq_a_d);
- if(config->pirq_e_h)
+ if (config->pirq_e_h)
pci_write_config32(dev, 0x68, config->pirq_e_h);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 326a9e5..f4ab2f6 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c
index fc41645..e018320 100644
--- a/src/southbridge/intel/i82801ex/i82801ex.c
+++ b/src/southbridge/intel/i82801ex/i82801ex.c
@@ -12,10 +12,10 @@ void i82801ex_enable(device_t dev)
/* See if we are behind the i82801ex pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
- if((dev->path.pci.devfn &0xf8)== 0xf8) {
+ if ((dev->path.pci.devfn &0xf8)== 0xf8) {
index = dev->path.pci.devfn & 7;
}
- else if((dev->path.pci.devfn &0xf8)== 0xe8) {
+ else if ((dev->path.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.pci.devfn & 7) +8;
}
if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 9cb6f39..2fcb83d 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -118,7 +118,7 @@ static void sata_init(struct device *dev)
/* Restrict ports - 0 and 2 only available */
ports &= 0x5;
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
/* Allow both Legacy and Native mode */
pci_write_config8(dev, 0x09, 0x8f);
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index b128280..e76087c 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
/* IOTRAP(0) SMIC: currently unused */
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 4f30865..5f1a44f 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d4fbed4..d11d531 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index ffeb8a2..98cd0bc 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -91,7 +91,7 @@ static void sata_init(struct device *dev)
/* SATA Initialization register */
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index a7c3319..462670e 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -105,7 +105,7 @@ static int codec_detect(u8 *base)
dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
- if(dword==0) {
+ if (dword==0) {
printk(BIOS_DEBUG, "No codec!\n");
return 0;
}
@@ -184,7 +184,7 @@ static u32 verb_data[] = {
static unsigned find_verb(u32 viddid, u32 **verb)
{
- if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
+ if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
*verb = (u32 *)verb_data;
return sizeof(verb_data)/sizeof(u32);
}
@@ -268,8 +268,8 @@ static void aza_init(struct device *dev)
printk(BIOS_DEBUG, "****** Azalia PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0){
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0){
printk(BIOS_DEBUG, "\n%02x: ", i);
}
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index f3fa079..6b939e7 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -148,8 +148,8 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
printk(BIOS_DEBUG, "****** IDE PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 0a5adf0..ef26745 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -139,7 +139,7 @@ static void lpc_init(device_t dev)
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
- if( byte != byte_old) {
+ if ( byte != byte_old) {
outb(byte, 0x70);
}
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index cd376ab..2144350 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -73,7 +73,7 @@ static void readApcMacAddr(void)
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
printk(BIOS_DEBUG, "MAC addr in APC = ");
- for(i = 0x9 ; i <=0xe ; i++)
+ for (i = 0x9 ; i <=0xe ; i++)
{
printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
}
@@ -98,7 +98,7 @@ static void set_apc(struct device *dev)
outl(0x80001048,0xcf8);
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
- for(i = 0 ; i <3; i++)
+ for (i = 0 ; i <3; i++)
{
addr=0x9+2*i;
writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
@@ -142,11 +142,11 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
mdelay(10);
- for(i=0 ; i <= LoopNum; i++)
+ for (i=0 ; i <= LoopNum; i++)
{
ulValue=read32(base + 0x3c);
- if(!(ulValue & 0x0080)) //BIT_7
+ if (!(ulValue & 0x0080)) //BIT_7
break;
mdelay(100);
@@ -154,7 +154,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
mdelay(50);
- if(i==LoopNum) data=0x10000;
+ if (i==LoopNum) data=0x10000;
else{
ulValue=read32(base + 0x3c);
data = ((ulValue & 0xffff0000) >> 16);
@@ -205,13 +205,13 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
// Scan all PHY address(0 ~ 31) to find a valid PHY
- for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
+ for (PhyAddress = 0; PhyAddress < 32; PhyAddress++)
{
usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
// Found a valid PHY
- if((usData != 0x0) && (usData != 0xffff))
+ if ((usData != 0x0) && (usData != 0xffff))
{
bFoundPhy = TRUE;
break;
@@ -219,7 +219,7 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
}
- if(!bFoundPhy)
+ if (!bFoundPhy)
{
printk(BIOS_DEBUG, "PHY not found !!!! \n");
}
@@ -260,7 +260,7 @@ static void nic_init(struct device *dev)
res = find_resource(dev, 0x10);
- if(!res)
+ if (!res)
{
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
@@ -268,7 +268,7 @@ static void nic_init(struct device *dev)
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "NIC base address %p\n",base);
- if(!(val=phy_detect(base,&PhyAddr)))
+ if (!(val=phy_detect(base,&PhyAddr)))
{
printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
return;
@@ -276,7 +276,7 @@ static void nic_init(struct device *dev)
ulValue=read32(base + 0x38L); // check EEPROM existing
- if((ulValue & 0x0002))
+ if ((ulValue & 0x0002))
{
// read MAC address from EEPROM at first
@@ -311,8 +311,8 @@ static void nic_init(struct device *dev)
printk(BIOS_DEBUG, "****** NIC PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c
index 197f4d2..eb69ab0 100644
--- a/src/southbridge/sis/sis966/sata.c
+++ b/src/southbridge/sis/sis966/sata.c
@@ -150,8 +150,8 @@ for (i=0;i<10;i++){
printk(BIOS_DEBUG, "****** SATA PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c
index 95f01d1..64398e2 100644
--- a/src/southbridge/sis/sis966/usb.c
+++ b/src/southbridge/sis/sis966/usb.c
@@ -75,8 +75,8 @@ static void usb_init(struct device *dev)
printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index 5bad6b3..8c34723 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -72,7 +72,7 @@ static void usb2_init(struct device *dev)
//-------------- enable USB2.0 (SiS7002) ----------------------
i = 0;
- while(SiS_SiS7002_init[i][0] != 0)
+ while (SiS_SiS7002_init[i][0] != 0)
{
temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
temp8 &= SiS_SiS7002_init[i][1];
@@ -82,7 +82,7 @@ static void usb2_init(struct device *dev)
};
res = find_resource(dev, 0x10);
- if(!res)
+ if (!res)
return;
base = res2mmio(res, 0, 0);
@@ -94,8 +94,8 @@ static void usb2_init(struct device *dev)
printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
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