[coreboot-gerrit] Patch set updated for coreboot: src/cpu: space required before the open parenthesis '('
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Aug 22 13:06:27 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16286
-gerrit
commit c9d5b69f1d6528660e88cdc438c2b526689f7a5d
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Aug 21 17:33:56 2016 +0200
src/cpu: space required before the open parenthesis '('
Change-Id: I7fb9bfcaeec0b9dfd0695d2b2d398fd01091f6bc
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/cpu/amd/dualcore/amd_sibling.c | 20 ++++++++++----------
src/cpu/amd/dualcore/dualcore.c | 6 +++---
src/cpu/amd/dualcore/dualcore_id.c | 2 +-
src/cpu/amd/family_10h-family_15h/processor_name.c | 2 +-
src/cpu/amd/model_fxx/powernow_acpi.c | 6 +++---
src/cpu/amd/model_fxx/processor_name.c | 8 ++++----
src/cpu/amd/mtrr/amd_mtrr.c | 6 +++---
src/cpu/amd/quadcore/amd_sibling.c | 12 ++++++------
src/cpu/amd/quadcore/quadcore_id.c | 2 +-
src/cpu/intel/hyperthreading/intel_sibling.c | 2 +-
src/cpu/intel/microcode/microcode.c | 2 +-
src/cpu/intel/speedstep/acpi.c | 2 +-
src/cpu/via/nano/nano_init.c | 8 ++++----
src/cpu/via/nano/update_ucode.c | 18 +++++++++---------
src/cpu/x86/lapic/lapic_cpu_init.c | 14 +++++++-------
src/cpu/x86/pae/pgtbl.c | 4 ++--
16 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index e0723ce..8c299b0 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -37,11 +37,11 @@ static int get_max_siblings(int nodes)
int siblings=0;
//get max siblings from all the nodes
- for(nodeid=0; nodeid<nodes; nodeid++){
+ for (nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
- if(siblings < j) {
+ if (siblings < j) {
siblings = j;
}
}
@@ -55,7 +55,7 @@ static void enable_apic_ext_id(int nodes)
int nodeid;
//enable APIC_EXIT_ID all the nodes
- for(nodeid=0; nodeid<nodes; nodeid++){
+ for (nodeid=0; nodeid<nodes; nodeid++){
uint32_t val;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
val = pci_read_config32(dev, 0x68);
@@ -82,9 +82,9 @@ unsigned get_apicid_base(unsigned ioapic_num)
siblings = get_max_siblings(nodes);
- if(bsp_apic_id > 0) { // io apic could start from 0
+ if (bsp_apic_id > 0) { // io apic could start from 0
return 0;
- } else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
+ } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
return 1;
}
@@ -92,11 +92,11 @@ unsigned get_apicid_base(unsigned ioapic_num)
#if 0
//it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it.
- if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
+ if (nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
//we need to check if e0 single core is there
int i;
- for(i=0; i<nodes; i++) {
- if(is_e0_later_in_bsp(i)) {
+ for (i=0; i<nodes; i++) {
+ if (is_e0_later_in_bsp(i)) {
siblings = 1;
break;
}
@@ -106,7 +106,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
//Construct apicid_base
- if((!disable_siblings) && (siblings>0) ) {
+ if ((!disable_siblings) && (siblings>0) ) {
/* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel
and the kernel will try to get one that is small than 16 to make io apic work.
I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
@@ -120,7 +120,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
apicid_base = nodes;
}
- if((apicid_base+ioapic_num-1)>0xf) {
+ if ((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index a545762..56f7dcc 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -18,7 +18,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
static inline uint8_t set_apicid_cpuid_lo(void)
{
#if !CONFIG_K8_REV_F_SUPPORT
- if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
+ if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set
#endif
// set the NB_CFG[54]=1; why the OS will be happy with that ???
@@ -55,8 +55,8 @@ static inline void start_other_cores(void)
nodes = get_nodes();
- for(nodeid=0; nodeid<nodes; nodeid++) {
- if( get_core_num_in_bsp(nodeid) > 0) {
+ for (nodeid=0; nodeid<nodes; nodeid++) {
+ if ( get_core_num_in_bsp(nodeid) > 0) {
real_start_other_core(nodeid);
}
}
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index 4fcedae..bbfdd51 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -26,7 +26,7 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
{
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
- if( nb_cfg_54) {
+ if ( nb_cfg_54) {
// when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>CORE_ID_BIT);
diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c
index 3d92ee2..bda8409 100644
--- a/src/cpu/amd/family_10h-family_15h/processor_name.c
+++ b/src/cpu/amd/family_10h-family_15h/processor_name.c
@@ -331,7 +331,7 @@ int init_processor_name(void)
processor_name_string = unknown2;
/* String 2 */
- for(i = 0; str2[i].value; i++) {
+ for (i = 0; str2[i].value; i++) {
if ((str2[i].Pg == Pg) &&
((str2[i].NC == NC) || !str2_checkNC) &&
(str2[i].String == String2)) {
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index d64c6d9..52138a1 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -775,7 +775,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
cpuid1 = cpuid(0x80000007);
- if((cpuid1.edx & 0x6)!=0x6) {
+ if ((cpuid1.edx & 0x6)!=0x6) {
printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
return;
}
@@ -845,7 +845,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
Pstate_vid[0] = Max_vid;
Pstate_power[0] = data->pwr * 100;
- for(Pstate_num = 1;
+ for (Pstate_num = 1;
(Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0);
Pstate_num++) {
Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
@@ -862,7 +862,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* Loop over all CPU's */
for (dev = 0x18; dev < 0x1c; dev++) {
- if(dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL)
+ if (dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL)
continue;
for (i = 0; i < (cmp_cap + 1); i++) {
diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c
index 2e2ad39..60dbf6e 100644
--- a/src/cpu/amd/model_fxx/processor_name.c
+++ b/src/cpu/amd/model_fxx/processor_name.c
@@ -118,10 +118,10 @@ int init_processor_name(void)
EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
BrandId = cpuid_ebx(0x80000001) & 0xffff;
- if(!EightBitBrandId && !BrandId) {
+ if (!EightBitBrandId && !BrandId) {
BrandTableIndex = 0;
NN = 0xffffff;
- } else if(!EightBitBrandId) {
+ } else if (!EightBitBrandId) {
BrandTableIndex = (BrandId >> 6) & 0x3f; // BrandId[11:6]
NN = BrandId & 0x3f; // // BrandId[6:0]
} else {
@@ -392,7 +392,7 @@ int init_processor_name(void)
*/
for (i=0; i<47; i++) { // 48 -1
- if(program_string[i] == program_string[i+1]) {
+ if (program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
#if !CONFIG_K8_REV_F_SUPPORT
case 'X': ModelNumber = 22+ NN; break;
@@ -412,7 +412,7 @@ int init_processor_name(void)
#endif
}
- if(ModelNumber && ModelNumber < 100) {
+ if (ModelNumber && ModelNumber < 100) {
// No idea what to do with RR=100. According
// to the revision guide this is possible.
//
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 6df8458..a0a5194 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -88,7 +88,7 @@ void amd_setup_mtrrs(void)
(((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0
((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
(((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables
- if(has_tom2wb)
+ if (has_tom2wb)
printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
/* Enable the access to AMD RdDram and WrDram extension bits */
@@ -109,7 +109,7 @@ void amd_setup_mtrrs(void)
sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
if (bsp_topmem2() > (uint64_t)1<<32) {
sys_cfg.lo |= SYSCFG_MSR_TOM2En;
- if(has_tom2wb)
+ if (has_tom2wb)
sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
}
@@ -117,7 +117,7 @@ void amd_setup_mtrrs(void)
* undefined side effects.
*/
msr.lo = msr.hi = 0;
- for(i = IORR_FIRST; i <= IORR_LAST; i++) {
+ for (i = IORR_FIRST; i <= IORR_LAST; i++) {
wrmsr(i, msr);
}
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index 397a3dd..22910f8 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -41,11 +41,11 @@ static u32 get_max_siblings(u32 nodes)
u32 siblings=0;
//get max siblings from all the nodes
- for(nodeid=0; nodeid<nodes; nodeid++){
+ for (nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = get_node_pci(nodeid, 3);
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
- if(siblings < j) {
+ if (siblings < j) {
siblings = j;
}
}
@@ -60,7 +60,7 @@ static void enable_apic_ext_id(u32 nodes)
u32 nodeid;
//enable APIC_EXIT_ID all the nodes
- for(nodeid=0; nodeid<nodes; nodeid++){
+ for (nodeid=0; nodeid<nodes; nodeid++){
u32 val;
dev = get_node_pci(nodeid, 0);
val = pci_read_config32(dev, 0x68);
@@ -82,7 +82,7 @@ u32 get_apicid_base(u32 ioapic_num)
siblings = get_max_siblings(sysconf.nodes);
- if(sysconf.bsp_apicid > 0) { // io apic could start from 0
+ if (sysconf.bsp_apicid > 0) { // io apic could start from 0
return 0;
} else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0
return 1;
@@ -93,7 +93,7 @@ u32 get_apicid_base(u32 ioapic_num)
//Construct apicid_base
- if((!disable_siblings) && (siblings>0) ) {
+ if ((!disable_siblings) && (siblings>0) ) {
/* for 8 way dual core, we will used up apicid 16:16, actually
16 is not allowed by current kernel and the kernel will try
to get one that is small than 16 to make io apic work. I don't
@@ -108,7 +108,7 @@ u32 get_apicid_base(u32 ioapic_num)
apicid_base = sysconf.nodes;
}
- if((apicid_base+ioapic_num-1)>0xf) {
+ if ((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
enable_apic_ext_id(sysconf.nodes);
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index b89aac7..cd83906 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -75,7 +75,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
* The apicid format varies based on processor revision
*/
apicid = (cpuid_ebx(1) >> 24) & 0xff;
- if( nb_cfg_54) {
+ if ( nb_cfg_54) {
if (fam15h && dual_node) {
id.coreid = apicid & 0x1f;
id.nodeid = (apicid & 0x60) >> 5;
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index de59c18..aeb5874 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -85,7 +85,7 @@ void intel_sibling_init(struct device *cpu)
}
/* I am the primary CPU start up my siblings */
- for(i = 1; i < siblings; i++) {
+ for (i = 1; i < siblings; i++) {
struct device_path cpu_path;
struct device *new;
/* Build the CPU device path */
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index b068141..0b0f21d 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -175,7 +175,7 @@ const void *intel_microcode_find(void)
}
/* Checkpoint 1: The microcode update falls within CBFS */
- if(update_size > microcode_len) {
+ if (update_size > microcode_len) {
#if !defined(__ROMCC__)
printk(BIOS_WARNING, "Microcode header corrupted!\n");
#endif
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 009d419..d85e487 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void)
{
struct device *cpu;
int count = 0;
- for(cpu = all_devices; cpu; cpu = cpu->next) {
+ for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
continue;
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index cdf0589..2918398 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -74,7 +74,7 @@ static void nano_set_max_fid_vid(void)
printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
cur_vid, min_vid, max_vid);
- if( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
+ if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
/* Set highest frequency and VID */
msr.lo = msr.hi;
msr.hi = 0;
@@ -121,7 +121,7 @@ static void nano_power(void)
wrmsr(MSR_IA32_MISC_ENABLE, msr);
u8 stepping = ( cpuid_eax(0x1) ) &0xf;
- if(stepping >= MODEL_NANO_3000_B0) {
+ if (stepping >= MODEL_NANO_3000_B0) {
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
/* Enable C1e, C2e, C3e, and C4e states */
msr = rdmsr(MSR_IA32_MISC_ENABLE);
@@ -143,7 +143,7 @@ static void nano_init(struct device *dev)
get_fms(&c, dev->device);
/* We didn't test this on the Nano 1000/2000 series, so warn the user */
- if(c.x86_mask < MODEL_NANO_3000_B0) {
+ if (c.x86_mask < MODEL_NANO_3000_B0) {
printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
"Please report any issues encountered. \n");
}
@@ -166,7 +166,7 @@ static void nano_init(struct device *dev)
* CBFS, we'll just get back with 0 updates. User choice FTW. */
unsigned int n_updates = nano_update_ucode();
- if(n_updates != 0){
+ if (n_updates != 0){
nano_power();
} else {
/* Changing the frequency or voltage without first updating the
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
index 44b074e..fc5c9d5 100644
--- a/src/cpu/via/nano/update_ucode.c
+++ b/src/cpu/via/nano/update_ucode.c
@@ -51,10 +51,10 @@ static void nano_print_ucode_info(const nano_ucode_header *ucode)
static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
{
/* We must have a valid signature */
- if(ucode->signature != NANO_UCODE_SIGNATURE)
+ if (ucode->signature != NANO_UCODE_SIGNATURE)
return NANO_UCODE_SIGNATURE_ERROR;
/* The size of the head must be exactly 12 double words */
- if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
+ if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
return NANO_UCODE_WRONG_SIZE;
/* How about a checksum ? Checksum must be 0
@@ -62,10 +62,10 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
int i;
u32 check = 0;
u32 *raw = (void*) ucode;
- for(i = 0 ; i < ((ucode->total_size) >> 2); i++) {
+ for (i = 0 ; i < ((ucode->total_size) >> 2); i++) {
check += raw[i];
}
- if(check != 0)
+ if (check != 0)
return NANO_UCODE_CHECKSUM_FAIL;
/* Made it here huh? Then it looks valid to us.
* If there's anything else wrong, the CPU will reject the update */
@@ -110,7 +110,7 @@ unsigned int nano_update_ucode(void)
ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
CBFS_TYPE_MICROCODE, &ucode_len);
/* Oops, did you forget to include the microcode ? */
- if(ucode_data == NULL) {
+ if (ucode_data == NULL) {
printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. "
"Aborting microcode updates\n");
return 0;
@@ -119,11 +119,11 @@ unsigned int nano_update_ucode(void)
/* We might do a lot of loops searching for the microcode updates, but
* keep in mind, nano_ucode_is_valid searches for the signature before
* doing anything else. */
- for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
+ for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
{
ucode_update_status stat;
const nano_ucode_header * ucode = (void *)(&ucode_data[i]);
- if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) {
+ if (nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) {
i++;
continue;
}
@@ -132,14 +132,14 @@ unsigned int nano_update_ucode(void)
* microcode */
i += (ucode->total_size >> 2);
/* Is the microcode compatible with our CPU? */
- if(ucode->applicable_fms != fms) continue;
+ if (ucode->applicable_fms != fms) continue;
/* For our most curious users */
nano_print_ucode_info(ucode);
/* The meat of the pie */
stat = nano_apply_ucode(ucode);
/* The user might want to know how the update went */
nano_print_ucode_status(stat);
- if(stat == UCODE_UPDATE_SUCCESS) n_updates++;
+ if (stat == UCODE_UPDATE_SUCCESS) n_updates++;
}
return n_updates;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index aaeceef..c220425 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -284,7 +284,7 @@ int start_cpu(struct device *cpu)
printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index,
(void *)stack_base, (void *)stack_end);
/* poison the stack */
- for(stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++)
+ for (stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++)
stack[i/sizeof(*stack)] = 0xDEADBEEF;
stacks[index] = stack;
/* Record the index and which CPU structure we are using */
@@ -307,7 +307,7 @@ int start_cpu(struct device *cpu)
if (result) {
result = 0;
/* Wait 1s or until the new CPU calls in */
- for(count = 0; count < 100000 ; count++) {
+ for (count = 0; count < 100000 ; count++) {
if (secondary_stack == 0) {
result = 1;
break;
@@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
struct device *cpu;
/* Loop through the cpus once getting them started */
- for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
+ for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
@@ -471,7 +471,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
/* Loop through the cpus once to let them run through SMM relocator */
- for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
+ for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
@@ -507,7 +507,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
/* Now loop until the other cpus have finished initializing */
old_active_count = 1;
active_count = atomic_read(&active_cpus);
- while(active_count > 1) {
+ while (active_count > 1) {
if (active_count != old_active_count) {
printk(BIOS_INFO, "Waiting for %d CPUS to stop\n",
active_count - 1);
@@ -517,7 +517,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
active_count = atomic_read(&active_cpus);
loopcount++;
}
- for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
+ for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
@@ -531,7 +531,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
}
printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
checkstack(_estack, 0);
- for(i = 1; i <= last_cpu_index; i++)
+ for (i = 1; i <= last_cpu_index; i++)
checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i);
}
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 9be415d..2dacc10 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -78,12 +78,12 @@ void *map_2M_page(unsigned long page)
pdp[2].addr_lo = ((uint32_t)&pd[512*2])|1;
pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1;
/* The first half of the page table is identity mapped */
- for(i = 0; i < 1024; i++) {
+ for (i = 0; i < 1024; i++) {
pd[i].addr_lo = ((i & 0x3ff) << 21)| 0xE3;
pd[i].addr_hi = 0;
}
/* The second half of the page table holds the mapped page */
- for(i = 1024; i < 2048; i++) {
+ for (i = 1024; i < 2048; i++) {
pd[i].addr_lo = ((window & 1) << 31) | ((i & 0x3ff) << 21) | 0xE3;
pd[i].addr_hi = (window >> 1);
}
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