[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Add PM methods to power gate PCIe

[Vaibhav Shankar (vaibhav.shankar@intel.com)]

Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16351

-gerrit

commit 62204b4c2be666290806ecf7ea77523e014fe931
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date:   Tue Aug 23 17:56:17 2016 -0700

    soc/intel/apollolake: Add PM methods to power gate PCIe
    
    Implement _ON/_OFF methods to power gate PCIe during S0ix
    entry.
    
    BUG=chrome-os-partner:55877
    TEST=Suspend and Resume using 'echo freeze > /sys/power/state'.
    System should resume with PCIE and wifi functional.
    
    Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
    Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
 src/soc/intel/apollolake/acpi/pcie.asl        | 153 ++++++++++++++++++++++++++
 src/soc/intel/apollolake/acpi/southbridge.asl |   3 +
 2 files changed, 156 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl
new file mode 100644
index 0000000..3a8bc8c
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pcie.asl
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpiolib.asl"
+
+Device (RP01)
+{
+	Name (_ADR, 0x00140000)
+	Name (_DDN, "PCIe-B 0")
+	Name (PWRG,1) /* power status */
+	Name (PDST, 0) /* present Detect status */
+
+
+	Method(_S0W, 0)
+	{
+		/* This method returns the lowest D-state supported by
+		 * PCIe root port during S0 state
+		 */
+
+		/* PMEs can be generated from D3Cold */
+		Return(4)
+	} /* End _S0W */
+
+	/* Dynamic Opregion needed to access registers
+	 * when the controller is in D3 cold
+	 */
+	OperationRegion(PX02, PCI_Config, 0x0, 0x380)
+	Field(PX02,AnyAcc, NoLock, Preserve)
+	{
+		Offset(0x5A), /* SLSTS- SLot status Register */
+		, 6,
+		PDS, 1, /* 6, Presence detect Change */
+		Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
+		, 2,
+		L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
+		L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
+		Offset(0xF4), /* BLKPLLEN */
+		, 10,
+		BPLL, 1,
+		Offset(0x338),
+		, 26,
+		BDQA, 1 /* BLKDQDA */
+	}
+
+	PowerResource(PXP, 0, 0)
+	{
+		/* Define the PowerResource for PCIe slot */
+		/*Method: _STA(), _ON(), _OFF() */
+
+		Method(_STA, 0, Serialized)
+		{
+			Store(PDS, PDST) /* store PDS */
+			If(LEqual(PDS,1))
+			{
+				If(LEqual(PWRG,1))
+				{
+					Return (1)
+				}
+				Else
+				{
+					Return (0)
+				}
+			}
+			Else
+			{
+				Return (0)
+			}
+		}
+
+		Method(_ON,0,Serialized) /* Turn on core power to PCIe Slot */
+		{
+			If(LEqual(PDST,1))
+			{ /* enter this condition if device is connected */
+				/*
+				 * De-assert PERST
+				/* loccal2 - PERST GPIO address
+				 * local1 - to toggle Tx pin of Dw0
+				 */
+				Store(\_SB.PRAD, Local2)
+				Store(\_SB.GPC0(Local2), Local1)
+				And(Local1, 0xFFFFFFFE , Local1)
+				\_SB.SPC0 (Local2, Local1)
+
+				Store(0, BDQA) /* Set BLKDQDA to 0 */
+				Store(0, BPLL) /* Set BLKPLLEN to 0 */
+				/* Set L23_Rdy to Detect Transition  (L23R2DT) */
+				Store(1, L23R)
+				Sleep(16)
+				Store(0, Local0)
+				/* Wait up to 16ms for transition to Detect */
+				While(L23R) {
+					If(Lgreater(Local0, 4))
+					{
+						Break
+					}
+					Sleep(16)
+					Increment(Local0)
+				}
+				Store(1, PWRG) /* Set 1 PWRG to indicate the device is on */
+			} /* End PDS condition check */
+		}
+
+		Method(_OFF,0,Serialized) /* Turn off core power to PCIe Slot */
+		{
+
+			/* Set L23_Rdy Entry Request (L23ER) */
+			If(LEqual(PDST,1))
+			{  /* enter this condition if device is connected */
+				Store(1, L23E)
+				Sleep(16) /* Delay for Link to transition */
+				Store(0, Local0)
+				While(L23E) {
+					If(Lgreater(Local0, 4))
+					{
+						Break
+					}
+					Sleep(16)
+					Increment(Local0)
+				}
+				Store(1, BDQA) /* Set BLKDQDA to 1 */
+				Store(1, BPLL) /* Set BLKPLLEN to 1 */
+
+				/*
+				 * Assert PERST
+				/* loccal2 - PERST GPIO address
+				 * local1 - to toggle Tx pin of Dw0
+				 */
+				Store(\_SB.PRAD, Local2)
+				Store(\_SB.GPC0(Local2), Local1)
+				Or(Local1, 0x1 , Local1)
+				\_SB.SPC0 (Local2, Local1)
+
+				/* Set 0 PWRG to indicate the device is off */
+				Store(0, PWRG)
+			} /* End PDS condition check */
+		} /* End of Method_OFF */
+	} /* End PXP */
+
+	Name(_PR0, Package(){PXP})
+	Name(_PR3, Package(){PXP})
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 391a531..d7ced0f 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
 
 #include <soc/gpe.h>
 
+/* PCIE device */
+#include "pcie.asl"
+
 /* LPSS device */
 #include "lpss.asl"