[coreboot-gerrit] New patch to review for coreboot: intel/skylake: PL2 override changes
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Jan 21 09:24:10 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13071
-gerrit
commit 9b2561b14157f16810cfc31f0e69a4fabd34dc75
Author: pchandri <preetham.chandrian at intel.com>
Date: Tue Jan 19 10:49:51 2016 -0800
intel/skylake: PL2 override changes
Override the default PL2 values with ones recommended by Intel.
BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.
CQ-DEPEND=CL:321392
Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a
Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f
Original-Signed-off-by: pchandri <preetham.chandrian at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/322454
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian at intel.com>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
src/mainboard/google/chell/devicetree.cb | 3 +++
src/mainboard/google/glados/devicetree.cb | 3 +++
src/mainboard/google/lars/devicetree.cb | 3 +++
src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++
4 files changed, 12 insertions(+)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index e401f26..ffc805c 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -167,6 +167,9 @@ chip soc/intel/skylake
# I2C4 is 1.8V
register "SerialIoI2cVoltage[4]" = "1"
+ # PL2 override 15W
+ register "tdp_pl2_override" = "15"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 03c46f4..c3aae8c 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -167,6 +167,9 @@ chip soc/intel/skylake
# I2C4 is 1.8V
register "SerialIoI2cVoltage[4]" = "1"
+ # PL2 override 15W
+ register "tdp_pl2_override" = "15"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index e858eea..c601507 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -161,6 +161,9 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}"
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 572dd43..73eced1 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -166,6 +166,9 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}"
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
device cpu_cluster 0 on
device lapic 0 on end
end
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