[coreboot-gerrit] New patch to review for coreboot: mainboard/intel/galileo: Enable Serial Output
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Fri Jan 29 03:22:17 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509
-gerrit
commit cdd8841dcb587440e6a37a570e298a4fe1f7f02d
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Tue Jan 26 15:20:45 2016 -0800
mainboard/intel/galileo: Enable Serial Output
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Specify the portion of ESRAM to be used by romstage
* Initialize the debug serial port
* Serial output indicates a successful test
TEST=Build and run on Galileo
CQ-DEPEND=CL:13445
Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/mainboard/intel/galileo/Kconfig | 9 +++++++++
src/mainboard/intel/galileo/Makefile.inc | 2 ++
src/mainboard/intel/galileo/com_init.c | 26 ++++++++++++++++++++++++++
3 files changed, 37 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index dd2d1bb..6fe9abc 100755
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -18,9 +18,18 @@ if BOARD_INTEL_GALILEO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
+ select ENABLE_BUILTIN_HSUART1
select PLATFORM_USES_FSP1_1
select SOC_INTEL_QUARK
+config DCACHE_RAM_BASE
+ hex
+ default 0x80070000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x00008000
+
if PLATFORM_USES_FSP1_1
config FSP_IMAGE_ID_STRING
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
index 2c4be88..11010eb 100755
--- a/src/mainboard/intel/galileo/Makefile.inc
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -15,6 +15,8 @@
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c
+
# Add the FSP binary to the cbfs image
ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y)
cbfs-files-y += fsp.bin
diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c
new file mode 100644
index 0000000..3cf4cd6
--- /dev/null
+++ b/src/mainboard/intel/galileo/com_init.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/car.h>
+#include <device/pci.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, UART_BASE_ADDRESS);
+}
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