[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: GPIO_TIER1_SCI_EN
Shaunak Saha (shaunak.saha@intel.com)
gerrit at coreboot.org
Wed Jul 13 08:48:49 CEST 2016
Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15612
-gerrit
commit c1eeb0b4e05a3a6c8197f7fbec5f91a497d98faa
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Mon Jul 11 16:03:52 2016 -0700
soc/intel/apollolake: GPIO_TIER1_SCI_EN
This patch adds the support for gpio_tier1_sci_en bit.This
bit needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
src/soc/intel/apollolake/include/soc/pm.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 99f922f..68d72e6 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -151,6 +151,12 @@
#define SLEEP_STATE_S3 3
#define SLEEP_STATE_S5 5
+/*
+ * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
+ * and/or an SCI or SMI#.
+ */
+#define GPIO_TIER_1_SCI (1 << 15)
+
/* Track power state from reset to log events. */
struct chipset_power_state {
uint16_t pm1_sts;
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