[coreboot-gerrit] New patch to review for coreboot: intel car: Unify whitespace and comment fixes
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Jul 20 15:09:07 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15759
-gerrit
commit a1c5a57f77c52fad950755def83721a607be0781
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Jul 20 12:50:20 2016 +0300
intel car: Unify whitespace and comment fixes
Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/car/cache_as_ram_ht.inc | 2 +-
src/cpu/intel/haswell/cache_as_ram.inc | 11 +++++------
src/cpu/intel/model_2065x/cache_as_ram.inc | 8 ++++----
src/cpu/intel/model_206ax/cache_as_ram.inc | 8 ++++----
src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +-
5 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 84a55c7..0abda49 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -288,7 +288,7 @@ no_msr_11e:
invd
movl %eax, %cr0
- /* Clear the cache memory reagion. */
+ /* Clear the cache memory region. This will also fill up the cache. */
cld
xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 2ccef78..3349883 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -30,8 +30,7 @@
#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
-#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS
-#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define NoEvictMod_MSR 0x2e0
@@ -96,7 +95,7 @@ clear_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -108,7 +107,7 @@ clear_mtrrs:
andl $~2, %eax
wrmsr
- /* Clear the cache memory region. This will also fill up the cache */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
@@ -135,8 +134,8 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index e6d95d5..093c784 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -101,7 +101,7 @@ clear_var_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -113,7 +113,7 @@ clear_var_mtrrs:
andl $~2, %eax
wrmsr
- /* Clear the cache memory region. This will also fill up the cache */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
@@ -140,8 +140,8 @@ clear_var_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index a1f5cc9..2757c55 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -93,7 +93,7 @@ clear_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -105,7 +105,7 @@ clear_mtrrs:
andl $~2, %eax
wrmsr
- /* Clear the cache memory region. This will also fill up the cache */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
@@ -132,8 +132,8 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index edd9e6c..9ae217c 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -83,7 +83,7 @@ clear_mtrrs:
invd
movl %eax, %cr0
- /* Clear the cache memory reagion. */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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