[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Enable LPSS IOSF PMCTL S0ix

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055

-gerrit

commit 95561bbab7a9534824e481a5eb6e7a25acdbf5a5
Author: Saurabh Satija <saurabh.satija at intel.com>
Date:   Tue May 3 15:15:31 2016 -0700

    soc/apollolake: Enable LPSS IOSF PMCTL S0ix
    
    Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
    Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/apollolake/chip.c | 2 ++
 src/soc/intel/apollolake/chip.h | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f56e1f2..6df3c4b 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -108,6 +108,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 
 	cfg = dev->chip_info;
 
+	silconfig->S0ixEnable = cfg->S0ixEnable;
+
 	silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
 	silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
 	silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index d74084e..1a30eb0 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -42,6 +42,9 @@ struct soc_intel_apollolake_config {
 
 	/* Configure serial IRQ (SERIRQ) line. */
 	enum serirq_mode serirq_mode;
+
+	/* Configure LPSS IOSF PMCTL S0ix Enable */
+	uint8_t S0ixEnable;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */