[coreboot-gerrit] Patch merged into coreboot/master: arch/riscv: Compile with -mcmodel=medany

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1282b8d99692ddfff5b78b03938b9b3555b17c00
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri Jun 10 19:35:15 2016 +0200

    arch/riscv: Compile with -mcmodel=medany
    
    In the default (medlow) code model, pointers are loaded with a lui, addi
    instruction sequence:
    
    	lui	a0, 0xNNNNN
    	addi	a0, a0, 0xNNN
    
    Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't
    load pointers just above 0x80000000, where RISC-V's RAM now lives.
    
    The medany code model gets around this restriction by loading pointers
    trough auipc and addi:
    
    	auipc	a0, 0xNNNNN
    	addi	a0, a0, 0xNNN
    
    This way, any pointer within the current pc ±2G can be loaded, which is
    by far sufficient for coreboot.
    
    Change-Id: I77350d9218a687284c1337d987765553cf915a22
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
    Reviewed-on: https://review.coreboot.org/15148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See https://review.coreboot.org/15148 for details.

-gerrit