[coreboot-gerrit] Patch merged into coreboot/master: riscv-spike: Replace custom UART with a memory-mapped 8250

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d15e9aaa48d4382de827522c1020edc63fb135f2
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri Jun 10 19:35:16 2016 +0200

    riscv-spike: Replace custom UART with a memory-mapped 8250
    
    Since the HTIF is a non-standard interface, and coreboot already has a
    8250 driver, I started implementing an 8250 core for spike[1].
    
    [1]: https://github.com/riscv/riscv-isa-sim/pull/53
    
    Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
    Reviewed-on: https://review.coreboot.org/15150
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See https://review.coreboot.org/15150 for details.

-gerrit