[coreboot-gerrit] New patch to review for coreboot: Fix some cbmem.h includes

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15196

-gerrit

commit e01368731cdb60c87a9a1d398efee6df357290e6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jun 15 06:07:55 2016 +0300

    Fix some cbmem.h includes
    
    Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/haswell/romstage.c                     | 2 +-
 src/cpu/intel/model_2065x/cache_as_ram.inc           | 1 -
 src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9932a50..9c08aa1 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/stages.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
-#include <cbfs.h>
+#include <cbmem.h>
 #include <romstage_handoff.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 6fa3eb8..269fbef 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
index fcd2d3b..7349af8 100644
--- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 #define CACHE_AS_RAM_SIZE 0x10000
 #define CACHE_AS_RAM_BASE 0xd0000