[coreboot-gerrit] New patch to review for coreboot: intel/model_206ax: Move platform specific defines
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Jun 15 05:37:00 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15197
-gerrit
commit d1629672c09403434af7af40e8b24458155de64d
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Jun 15 06:15:46 2016 +0300
intel/model_206ax: Move platform specific defines
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/model_206ax/cache_as_ram.inc | 2 +-
src/include/cbmem.h | 13 ++-----------
src/northbridge/intel/sandybridge/sandybridge.h | 6 ++++++
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 358ba75..56feab9 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -17,8 +17,8 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#include <cbmem.h>
#include <arch/acpi.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 2182ce7..5b75db0 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -19,18 +19,12 @@
#include <commonlib/cbmem_id.h>
#include <rules.h>
-/* Delegation of resume backup memory so we don't have to
- * (slowly) handle backing up OS memory in romstage.c
- */
-#define CBMEM_BOOT_MODE 0x610
-#define CBMEM_RESUME_BACKUP 0x614
-#define CBMEM_FSP_HOB_PTR 0x614
-
-#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
#include <boot/coreboot_tables.h>
+#define CBMEM_FSP_HOB_PTR 0x614
+
struct cbmem_entry;
/*
@@ -151,7 +145,4 @@ void set_top_of_ram(uint64_t ramtop);
void backup_top_of_ram(uint64_t ramtop);
#endif
-#endif /* __ASSEMBLER__ */
-
-
#endif /* _CBMEM_H_ */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index af5bd48..7b0efd1 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -196,6 +196,12 @@
#define DMIDRCCFG 0xeb4 /* 32bit */
+/* Delegation of resume backup memory so we don't have to
+ * (slowly) handle backing up OS memory in romstage.c
+ */
+#define CBMEM_BOOT_MODE 0x610
+#define CBMEM_RESUME_BACKUP 0x614
+
#ifndef __ASSEMBLER__
static inline void barrier(void) { asm("" ::: "memory"); }
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