New patch to review for coreboot: SPD module’s voltage

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15202

-gerrit

commit d12a4d6eae6c047dd426bc9221ee2551bd207853
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Wed Jun 15 19:05:11 2016 +0200

    SPD module’s voltage
    
    regarding JEDEC_DDR2_SPD_Specification_Rev1.3 page 10,
    SSTL 1.8V Interface Level added
    
    Change-Id: I0112a85f557826b629109e212dbbc752aeda305d
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/include/spd.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/include/spd.h b/src/include/spd.h
index 7aaf4dd..62a7494 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -125,6 +125,7 @@ enum spd_memory_type {
 #define SPD_VOLTAGE_HSTL                 2 /* HSTL 1.5 */
 #define SPD_VOLTAGE_SSTL3                3 /* SSTL 3.3 */
 #define SPD_VOLTAGE_SSTL2                4 /* SSTL 2.5 */
+#define SPD_VOLTAGE_SSTL1		 5 /* SSTL 1.8 */
 
 /* SPD_DIMM_CONFIG_TYPE values. */
 #define ERROR_SCHEME_NONE                0