[coreboot-gerrit] Patch set updated for coreboot: nb/intel/sandybridge/raminit: Code cleanup

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15184

-gerrit

commit 7afcce6ac7769b4cb08ea3dc140c396e343ca10e
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Tue Jun 14 20:07:32 2016 +0200

    nb/intel/sandybridge/raminit: Code cleanup
    
    Set the phase coding for CLK pins.
    The value can be calculated from current DDR frequency.
    
    Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 49cffc2..35b95db 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -655,7 +655,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[0] = 18;
 		ctrl->timC_offset[1] = 7;
 		ctrl->timC_offset[2] = 7;
-		ctrl->reg_c14_offset = 16;
 		ctrl->reg_320c_range_threshold = 13;
 	} else if (ctrl->tCK <= TCK_933MHZ) {
 		ctrl->tCK = TCK_933MHZ;
@@ -665,7 +664,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[0] = 15;
 		ctrl->timC_offset[1] = 6;
 		ctrl->timC_offset[2] = 6;
-		ctrl->reg_c14_offset = 14;
 		ctrl->reg_320c_range_threshold = 15;
 	} else if (ctrl->tCK <= TCK_800MHZ) {
 		ctrl->tCK = TCK_800MHZ;
@@ -675,7 +673,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[0] = 14;
 		ctrl->timC_offset[1] = 5;
 		ctrl->timC_offset[2] = 5;
-		ctrl->reg_c14_offset = 12;
 		ctrl->reg_320c_range_threshold = 15;
 	} else if (ctrl->tCK <= TCK_666MHZ) {
 		ctrl->tCK = TCK_666MHZ;
@@ -685,7 +682,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[0] = 11;
 		ctrl->timC_offset[1] = 4;
 		ctrl->timC_offset[2] = 4;
-		ctrl->reg_c14_offset = 10;
 		ctrl->reg_320c_range_threshold = 16;
 	} else if (ctrl->tCK <= TCK_533MHZ) {
 		ctrl->tCK = TCK_533MHZ;
@@ -695,7 +691,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[0] = 9;
 		ctrl->timC_offset[1] = 3;
 		ctrl->timC_offset[2] = 3;
-		ctrl->reg_c14_offset = 8;
 		ctrl->reg_320c_range_threshold = 17;
 	} else  {
 		ctrl->tCK = TCK_400MHZ;
@@ -705,10 +700,12 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[0] = 6;
 		ctrl->timC_offset[1] = 2;
 		ctrl->timC_offset[2] = 2;
-		ctrl->reg_c14_offset = 8;
 		ctrl->reg_320c_range_threshold = 17;
 	}
 
+	/* Initial phase between CLK/CMD pins */
+	ctrl->reg_c14_offset = (256000 / ctrl->tCK) / 66;
+
 	/* DLL_CONFIG_MDLL_W_TIMER */
 	ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;