[coreboot-gerrit] New patch to review for coreboot: intel/broadwell: Remove old USBDEBUG backup store in CAR

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15236

-gerrit

commit ed0a734ee1d96bf49b2615744d41cadb503fc8c0
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jun 15 16:01:16 2016 +0300

    intel/broadwell: Remove old USBDEBUG backup store in CAR
    
    Required EHCI state is maintained as a CAR_GLOBAL to have it
    properly migrated.
    
    Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/soc/intel/broadwell/romstage/cache_as_ram.inc | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index a636e9f..765f9af 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -26,7 +26,6 @@
 	(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 #define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
-#define USBDEBUG_VAR_SIZE  36 /* sizeof(struct ehci_debug_info) */
 
 /* Cache 4GB - MRC_SIZE_KB for MRC */
 #define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
@@ -166,9 +165,6 @@ clear_mtrrs:
 
 	/* Setup the stack. */
 	movl	$(CACHE_AS_RAM_LIMIT), %eax
-#if CONFIG_USBDEBUG
-	sub	$(USBDEBUG_VAR_SIZE), %eax
-#endif
 	movl	%eax, %esp
 
 	/* Restore the BIST result. */
@@ -193,15 +189,6 @@ before_romstage:
 
 	post_code(0x2f)
 
-	/* Copy global variable space (for USBDEBUG) to memory */
-#if CONFIG_USBDEBUG
-	cld
-	movl	$(CACHE_AS_RAM_LIMIT - USBDEBUG_VAR_SIZE), %esi
-	movl	$(CONFIG_RAMTOP - USBDEBUG_VAR_SIZE), %edi
-	movl	$USBDEBUG_VAR_SIZE, %ecx
-	rep	movsb
-#endif
-
 	post_code(0x30)
 
 	/* Disable cache. */