[coreboot-gerrit] New patch to review for coreboot: gru: kevin: initialize cr50 SPI interface

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15296

-gerrit

commit 05e0dc0743b90bdf258727566eb9e145b0e5582e
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Apr 8 20:18:17 2016 -0700

    gru: kevin: initialize cr50 SPI interface
    
    Set up the pins and initialize the driver.
    
    BRANCH=none
    BUG=chrome-os-partner:50645, chrome-os-partner:51537
    TEST=with the rest of the patches applied it is possible to
         communicate with the cr50.
    
    Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d
    Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/349852
    Original-Reviewed-by: Douglas Anderson <dianders at chromium.org>
---
 src/mainboard/google/gru/bootblock.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 19e2cde..0e485cf 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -64,9 +64,13 @@ void bootblock_mainboard_init(void)
 	write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
 	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
-	/* Set pinmux and configure EC flashrom. */
+	/* Set pinmux and configure EC SPI. */
 	write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);
 	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
 
+	/* Set pinmux and configure TPM SPI, which is not very fast. */
+	write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
+	rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
+
 	setup_chromeos_gpios();
 }