[coreboot-gerrit] Patch merged into coreboot/master: Skylake boards: Enabling HWP (hardware P state control)

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2a696c07b9cdcd484800596fb850f95260419d11
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Feb 8 17:19:10 2016 +0530

    Skylake boards: Enabling HWP (hardware P state control)
    
    This patch provides config options to enable/disable Intel SST
    (Speed Shift Technology).
    
    BUG=chrome-os-partner:47517
    BRANCH=None
    TEST=Booted kunimitsu/lars, verified HWP driver load successfully.
    
    CQ-DEPEND=CL:313107
    
    Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
    Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
    Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
    Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/326650
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Benson Leung <bleung at chromium.org>
    Reviewed-on: https://review.coreboot.org/13843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/13843 for details.

-gerrit