[coreboot-gerrit] Patch merged into coreboot/master: Skylake: Support Intel Speed Shift Technology based on config

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b7e69a2e561d557a7d243a15d91a5cede56e5eb8
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Feb 8 17:15:29 2016 +0530

    Skylake: Support Intel Speed Shift Technology based on config
    
    Intel Speed Shift Technology is a new mechanism that replaces
    Legacy P-state. ISST allows OS hints about energy/performance
    preference. H/W performs the actual P-state control (autonomous)
    
    1. Optimization frequency seclection for low residency workloads,
    no longer a static knee point.
    2. Optimized frequency selection for best energy to performance
    trade offs.
    3. Kick down frequency (from idle) fpr best responsiveness while
    taking energy consumption init account.
    
    Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
    which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
    and enable HWP accordingly.
    
    BUG=chrome-os-partner:47517
    BRANCH=None
    TEST=Booted kunimitsu and verify HWP getting enabled/disabled
    using Intel P-state driver.
    
    Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
    Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
    Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
    Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/313107
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Wenkai Du <wenkai.du at intel.com>
    Reviewed-on: https://review.coreboot.org/13835
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/13835 for details.

-gerrit