[coreboot-gerrit] New patch to review for coreboot: google/oak: Configure SPI_LEVEL_ENABLE pin for rev5

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13970

-gerrit

commit 6b534db3bc58698c37ed5736623094de59357008
Author: Yidi Lin <yidi.lin at mediatek.com>
Date:   Mon Dec 28 16:14:42 2015 +0800

    google/oak: Configure SPI_LEVEL_ENABLE pin for rev5
    
    Oak introduces a 1.8V to 3.3V level shifter for EC SPI bus after rev5.
    
    BRANCH=none
    BUG=none
    TEST=emerge-oak coreboot
    
    Change-Id: I71868b003fc71dee0532033299afc155a9fbec9c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 030b478fedf046a7b818696779299c591415fcbd
    Original-Change-Id: Ibff9705832700867279cb1b39b752b8f5f27cf33
    Original-Signed-off-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/320026
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/mainboard/google/oak/bootblock.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 49cf5dd..2c13b14 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -17,6 +17,7 @@
 #include <boardid.h>
 #include <bootblock_common.h>
 #include <delay.h>
+#include <gpio.h>
 #include <soc/gpio.h>
 #include <soc/i2c.h>
 #include <soc/mt6391.h>
@@ -79,6 +80,10 @@ void bootblock_mainboard_init(void)
 	/* set nor related GPIO */
 	nor_set_gpio_pinmux();
 
+	/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
+	if (board_id() > 4)
+		gpio_output(PAD_SRCLKENAI2, 1);
+
 	/* Init i2c bus 2 Timing register for TPM */
 	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);