[coreboot-gerrit] Patch set updated for coreboot: mainboard/pcengines/apu2: WIP - Add PC Engines APU2 mainboard
Philipp Deppenwiese (zaolin.daisuki@googlemail.com)
gerrit at coreboot.org
Fri Mar 18 13:46:58 CET 2016
Philipp Deppenwiese (zaolin.daisuki at googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14138
-gerrit
commit 43dfeb839bdc2fb0087a383f41814515f62a4cfb
Author: Philipp Deppenwiese <zaolin at das-labor.org>
Date: Fri Mar 18 13:34:27 2016 +0100
mainboard/pcengines/apu2: WIP - Add PC Engines APU2 mainboard
Currently WIP and not working !
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
---
src/device/dram/Makefile.inc | 1 +
src/mainboard/pcengines/apu1/Kconfig | 5 -
src/mainboard/pcengines/apu2/BiosCallOuts.c | 163 +++++++
src/mainboard/pcengines/apu2/Kconfig | 128 ++++++
src/mainboard/pcengines/apu2/Kconfig.name | 2 +
src/mainboard/pcengines/apu2/Makefile.inc | 45 ++
src/mainboard/pcengines/apu2/OptionsIds.h | 68 +++
src/mainboard/pcengines/apu2/PlatformGnbPcie.c | 122 ++++++
.../pcengines/apu2/PlatformGnbPcieComplex.h | 27 ++
src/mainboard/pcengines/apu2/acpi/gpe.asl | 80 ++++
src/mainboard/pcengines/apu2/acpi/ide.asl | 1 +
src/mainboard/pcengines/apu2/acpi/mainboard.asl | 37 ++
src/mainboard/pcengines/apu2/acpi/pci_int.asl | 471 +++++++++++++++++++++
src/mainboard/pcengines/apu2/acpi/routing.asl | 213 ++++++++++
src/mainboard/pcengines/apu2/acpi/sata.asl | 1 +
src/mainboard/pcengines/apu2/acpi/si.asl | 23 +
src/mainboard/pcengines/apu2/acpi/sleep.asl | 93 ++++
src/mainboard/pcengines/apu2/acpi/superio.asl | 28 ++
src/mainboard/pcengines/apu2/acpi/thermal.asl | 1 +
src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 36 ++
src/mainboard/pcengines/apu2/acpi_tables.c | 276 ++++++++++++
src/mainboard/pcengines/apu2/apu2.h | 42 ++
src/mainboard/pcengines/apu2/board_info.txt | 6 +
src/mainboard/pcengines/apu2/cmos.default | 13 +
src/mainboard/pcengines/apu2/cmos.layout | 126 ++++++
src/mainboard/pcengines/apu2/devicetree.cb | 92 ++++
src/mainboard/pcengines/apu2/dsdt.asl | 90 ++++
src/mainboard/pcengines/apu2/irq_tables.c | 104 +++++
src/mainboard/pcengines/apu2/mainboard.c | 163 +++++++
src/mainboard/pcengines/apu2/mptable.c | 198 +++++++++
src/mainboard/pcengines/apu2/romstage.c | 236 +++++++++++
.../pcengines/apu2/spd/HYNIX-2G-1333.spd.hex | 263 ++++++++++++
.../pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex | 257 +++++++++++
.../pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex | 258 +++++++++++
src/southbridge/amd/pi/hudson/Makefile.inc | 2 +
src/southbridge/amd/pi/hudson/early_setup.c | 16 +-
src/southbridge/amd/pi/hudson/fchgpio.c | 137 ++++++
src/southbridge/amd/pi/hudson/fchgpio.h | 44 ++
38 files changed, 3862 insertions(+), 6 deletions(-)
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index 05f440b..9571ac3 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1 +1,2 @@
romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c
+ramstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 2328776..60e92e2 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -63,11 +63,6 @@ config VGA_BIOS
bool
default n
-#config VGA_BIOS_FILE
-# string "VGA BIOS path and filename"
-# depends on VGA_BIOS
-# default "rom/video/OntarioGenericVbios.bin"
-
config VGA_BIOS_ID
string
default "1002,9802"
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
new file mode 100644
index 0000000..5dda286
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include "Ids.h"
+//#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#include "imc.h"
+#endif
+#include "hudson.h"
+#include <stdlib.h>
+#include <fchgpio.h>
+#include "apu2.h"
+#include <spd_cache.h> // for the apu2_ReadSpd_from_cbfs function
+
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_READ_SPD, apu2_ReadSpd_from_cbfs },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }
+
+
+/*
+ * Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM will fail to read the input temperature via I2C if other
+ * software switches the I2C address. AMD recommends using IMC
+ * to control fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = FALSE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, IMC etc.
+ */
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
+ if (StdHeader->Func == AMD_INIT_RESET) {
+ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
+ printk(BIOS_DEBUG, "\n%s in INIT RESET\n", __func__ );
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->FchReset.SataEnable = hudson_sata_enable();
+ FchParams->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci1Enable = FALSE;
+
+
+ } else if (StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+ /* Azalia Controller OEM Codec Table Pointer */
+ /* Azalia Controller Front Panel OEM Table Pointer */
+
+ // No audio support in this system
+ FchParams->Azalia.AzaliaEnable = AzDisable;
+
+ /* Fan Control */
+ oem_fan_control(FchParams);
+
+ /* XHCI configuration */
+ FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci1Enable = FALSE;
+
+ /* EHCI configuration */
+ FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+
+ /* sata configuration */
+ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+ FchParams->Sata.SataDevSlpPort1 = 0;
+
+ FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+ switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+ case SataRaid:
+ case SataAhci:
+ case SataAhci7804:
+ case SataLegacyIde:
+ FchParams->Sata.SataIdeMode = FALSE;
+ break;
+ case SataIde2Ahci:
+ case SataIde2Ahci7804:
+ default: /* SataNativeIde */
+ FchParams->Sata.SataIdeMode = TRUE;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ int index = 0;
+
+ if (info->MemChannelId > 0)
+ return AGESA_UNSUPPORTED;
+ if (info->SocketId != 0)
+ return AGESA_UNSUPPORTED;
+ if (info->DimmId != 0)
+ return AGESA_UNSUPPORTED;
+
+ /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/
+
+ if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0;
+ if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1;
+
+ printk(BIOS_INFO, "Reading SPD index %d\n", index);
+
+ if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
+ die("No SPD data\n");
+
+ Status = AGESA_SUCCESS;
+#endif
+ return Status;
+}
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
new file mode 100644
index 0000000..2dce547
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -0,0 +1,128 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2016 Eltan B.V.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_PCENGINES_APU2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_PI_00730F01
+ select NORTHBRIDGE_AMD_PI_00730F01
+ select SOUTHBRIDGE_AMD_PI_AVALON
+ select SUPERIO_NUVOTON_NCT5104D
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_8192
+ select SPD_CACHE
+ select HUDSON_DISABLE_IMC
+ select HAVE_OPTION_TABLE
+ select USE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+
+config MAINBOARD_DIR
+ string
+ default pcengines/apu2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PCEngines apu2"
+
+config SVI2_SLOW_SPEED
+ bool "SVI2 slow speed"
+ default n
+ help
+ Used when there are problems switching the VRM speed. By default
+ speed is 20 Mhz
+
+config SVI_WAIT_COMP_DIS
+ bool "Disable SVI2 controller waits for command completion"
+ default y
+ help
+ SVI2 controller will not wait for command completion from VRM
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
+config HUDSON_XHCI_ENABLE
+ bool
+ default y
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default n
+
+config AGESA_HEAP_MEMTEST
+ bool
+ default y
+
+config VGA_ROM_RUN
+ bool
+ default n
+
+config DUMP_GPIO_CONFIGURATION
+ bool "Dump FCH GPIO configuration in board finalize"
+ default n
+
+config DUMP_CLOCK_CONFIGURATION
+ bool "Dump FCH MISC configuration in board finalize"
+ default n
+
+config DUMP_LINK_CONFIGURATION
+ bool "Dump PCIe LINK configuration in board finalize"
+ default n
+
+config SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE
+ bool "enable uartc"
+ default n
+
+config SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE
+ bool "enable uartd"
+ default n
+
+endif # BOARD_PCENGINES_APU2
diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
new file mode 100644
index 0000000..ab19ee4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PCENGINES_APU2
+ bool "APU2"
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
new file mode 100644
index 0000000..002770b
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -0,0 +1,45 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2016 Eltan B.V.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+#romstage-y += agesawrapper.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+#ramstage-y += agesawrapper.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+
+# WIV20141001 START ADD SPD FROM FILE
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS) src/mainboard/$(MAINBOARDDIR)/Makefile.inc
+ echo " create SPD $@"
+ for f in $(SPD_DEPS); \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
+# WIV20141001 END ADD SPD FROM FILE
diff --git a/src/mainboard/pcengines/apu2/OptionsIds.h b/src/mainboard/pcengines/apu2/OptionsIds.h
new file mode 100644
index 0000000..d1d3dab
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/OptionsIds.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+
+//#define IDSOPT_TRACING_ENABLED TRUE
+//#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
+//#define IDS_DEBUG_PRINT_MASK (FCH_TRACE_ALL) // We just want to see the FCH stuff now
+//#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_TRACING_CONSOLE_REDIRECT_IO TRUE
+
+//#define IDSOPT_PERF_ANALYSIS TRUE
+//#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/pcengines/apu2/PlatformGnbPcie.c b/src/mainboard/pcengines/apu2/PlatformGnbPcie.c
new file mode 100644
index 0000000..284f1c6
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/PlatformGnbPcie.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+const PCIe_PORT_DESCRIPTOR PortList [] = {
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+const PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}
diff --git a/src/mainboard/pcengines/apu2/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu2/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..8f49a6d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/PlatformGnbPcieComplex.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include <Porting.h>
+#include <AGESA.h>
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl
new file mode 100644
index 0000000..31b9d0c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+// /* Azalia SCI event */
+// Method(_L1B) {
+// /* DBGO("\\_GPE\\_L1B\n") */
+// Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+// Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+// }
+} /* End Scope GPE */
diff --git a/src/mainboard/pcengines/apu2/acpi/ide.asl b/src/mainboard/pcengines/apu2/acpi/ide.asl
new file mode 100644
index 0000000..95d1db4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/ide.asl
@@ -0,0 +1 @@
+/* No IDE functionality */
diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
new file mode 100644
index 0000000..0141481
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/pci_int.asl b/src/mainboard/pcengines/apu2/acpi/pci_int.asl
new file mode 100644
index 0000000..1dcb255
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/pci_int.asl
@@ -0,0 +1,471 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized){
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ /* IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} */
+ IRQ(Level,ActiveLow,Exclusive){3, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PIRA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_SRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PIRB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PIRC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIRD) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRD, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRD)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PIRE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PIRF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(IRQP)
+// Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+// Device(INTG) {
+// Name(_HID, EISAID("PNP0C0F"))
+// Name(_UID, 7)
+//
+// Method(_STA, 0) {
+// if (PIRG) {
+// Return(0x0B) /* sata is invisible */
+// } else {
+// Return(0x09) /* sata is disabled */
+// }
+// } /* End Method(_SB.INTG._STA) */
+//
+// Method(_DIS ,0) {
+// /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+// } /* End Method(_SB.INTG._DIS) */
+//
+// Method(_PRS ,0) {
+// /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+// Return(IRQP)
+// } /* Method(_SB.INTG._CRS) */
+//
+// Method(_CRS ,0) {
+// /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+// CreateWordField(IRQB, 0x1, IRQN)
+// ShiftLeft(1, PIRG, IRQN)
+// Return(IRQB)
+// } /* Method(_SB.INTG._CRS) */
+//
+// Method(_SRS, 1) {
+// /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+// CreateWordField(ARG0, 1, IRQM)
+//
+// /* Use lowest available IRQ */
+// FindSetRightBit(IRQM, Local0)
+// if (Local0) {
+// Decrement(Local0)
+// }
+// Store(Local0, PIRG)
+// } /* End Method(_SB.INTG._SRS) */
+// } /* End Device(INTG) */
+//
+// Device(INTH) {
+// Name(_HID, EISAID("PNP0C0F"))
+// Name(_UID, 8)
+//
+// Method(_STA, 0) {
+// if (PIRH) {
+// Return(0x0B) /* sata is invisible */
+// } else {
+// Return(0x09) /* sata is disabled */
+// }
+// } /* End Method(_SB.INTH._STA) */
+//
+// Method(_DIS ,0) {
+// /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+// } /* End Method(_SB.INTH._DIS) */
+//
+// Method(_PRS ,0) {
+// /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+// Return(IRQP)
+// } /* Method(_SB.INTH._CRS) */
+//
+// Method(_CRS ,0) {
+// /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+// CreateWordField(IRQB, 0x1, IRQN)
+// ShiftLeft(1, PIRH, IRQN)
+// Return(IRQB)
+// } /* Method(_SB.INTH._CRS) */
+//
+// Method(_SRS, 1) {
+// /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+// CreateWordField(ARG0, 1, IRQM)
+//
+// /* Use lowest available IRQ */
+// FindSetRightBit(IRQM, Local0)
+// if (Local0) {
+// Decrement(Local0)
+// }
+// Store(Local0, PIRH)
+// } /* End Method(_SB.INTH._SRS) */
+// } /* End Device(INTH) */
diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl
new file mode 100644
index 0000000..37c01d0
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/routing.asl
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 0, INTC, 0 },
+
+#else // CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 44 },
+ Package(){0x0001FFFF, 1, 0, 45 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 24 },
+ Package(){0x0002FFFF, 1, 0, 25 },
+ Package(){0x0002FFFF, 2, 0, 26 },
+ Package(){0x0002FFFF, 3, 0, 27 },
+
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */
+
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 0, 0, 18 },
+
+#else //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+})
+
+Name(PS2, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS2, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GFX */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 24 },
+ Package(){0x0000FFFF, 1, 0, 25 },
+ Package(){0x0000FFFF, 2, 0, 26 },
+ Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 0 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 28 },
+ Package(){0x0000FFFF, 1, 0, 29 },
+ Package(){0x0000FFFF, 2, 0, 30 },
+ Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 1 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 32 },
+ Package(){0x0000FFFF, 1, 0, 33 },
+ Package(){0x0000FFFF, 2, 0, 34 },
+ Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 2 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 36 },
+ Package(){0x0000FFFF, 1, 0, 37 },
+ Package(){0x0000FFFF, 2, 0, 38 },
+ Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 3 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 40 },
+ Package(){0x0000FFFF, 1, 0, 41 },
+ Package(){0x0000FFFF, 2, 0, 42 },
+ Package(){0x0000FFFF, 3, 0, 43 },
+})
diff --git a/src/mainboard/pcengines/apu2/acpi/sata.asl b/src/mainboard/pcengines/apu2/acpi/sata.asl
new file mode 100644
index 0000000..f675323
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/sata.asl
@@ -0,0 +1 @@
+/* No SATA functionality */
diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl
new file mode 100644
index 0000000..2923471
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl
new file mode 100644
index 0000000..4460aed
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+*s Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ \_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ Store(1,USBS)
+
+ \_SB.AWAK(Arg0)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl
new file mode 100644
index 0000000..be62853
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/superio.asl
@@ -0,0 +1,28 @@
+/* We don't have a real SIO but lets define the serial port here, this is where it belongs */
+
+ Device (COM1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+ Name (_ADR, 0)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+// IRQNoFlags () {}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0, 0) {
+ IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+// IRQNoFlags () {4}
+ IRQNoFlags () {}
+ }
+ EndDependentFn ()
+ })
+ }
diff --git a/src/mainboard/pcengines/apu2/acpi/thermal.asl b/src/mainboard/pcengines/apu2/acpi/thermal.asl
new file mode 100644
index 0000000..edb1daf
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/thermal.asl
@@ -0,0 +1 @@
+/* No thermal zone functionality */
diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
new file mode 100644
index 0000000..1643fe7
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c
new file mode 100644
index 0000000..84a33f8
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi_tables.c
@@ -0,0 +1,276 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ /* TODO: Remove the hardcode */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+ 0xFEC20000, 24);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+#if FALSE
+unsigned long acpi_fill_hest(acpi_hest_t *hest)
+{
+ void *addr, *current;
+
+ /* Skip the HEST header. */
+ current = (void *)(hest + 1);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ return (unsigned long)current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* Not implemented */
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *alib;
+ acpi_header_t *ivrs;
+ acpi_hest_t *hest;
+
+ /* Align ACPI tables to 16 bytes */
+ start = ALIGN(start, 16);
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* DSDT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; /* it will used by fadt */
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ /* it needs 64 byte alignment */
+ current = ALIGN(current, 64);
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current; /* it will be used by fadt */
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* HEST */
+ current = ALIGN(current, 8);
+ hest = (acpi_hest_t *)current;
+ acpi_write_hest((void *)current);
+ acpi_add_table(rsdp, (void *)current);
+ current += ((acpi_header_t *)current)->length;
+
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
+ ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
+ if (ivrs != NULL) {
+ memcpy((void *)current, ivrs, ivrs->length);
+ ivrs = (acpi_header_t *) current;
+ current += ivrs->length;
+ acpi_add_table(rsdp, ivrs);
+ } else {
+ printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
+ }
+
+ /* SRAT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
+ }
+
+ /* SLIT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
+ }
+
+ /* ALIB */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
+ alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+ if (alib != NULL) {
+ memcpy((void *)current, alib, alib->length);
+ alib = (acpi_header_t *) current;
+ current += alib->length;
+ acpi_add_table(rsdp, (void *)alib);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
+ }
+
+ /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
+ /* SSDT */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy((void *)current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
+#endif //FALSE
diff --git a/src/mainboard/pcengines/apu2/apu2.h b/src/mainboard/pcengines/apu2/apu2.h
new file mode 100644
index 0000000..847b5df
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/apu2.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+
+ *
+ * Copyright (C) 2015 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#define APU2_SPD_STRAP0_GPIO 0x40 // GPIO49
+#define APU2_SPD_STRAP0_FUNC Function2
+#define APU2_SPD_STRAP1_GPIO 0x41 // GPIO50
+#define APU2_SPD_STRAP1_FUNC Function2
+#define APU2_PE3_RST_L_GPIO 0x42 // GPIO51
+#define APU2_PE3_RST_L_FUNC Function2
+#define APU2_PE4_RST_L_GPIO 0x43 // DEVSLP[0]/GPIO59
+#define APU2_PE4_RST_L_FUNC Function3
+#define APU2_LED1_L_GPIO 0x44 // GPIO57
+#define APU2_LED1_L_FUNC Function1
+#define APU2_LED2_L_GPIO 0x45 // GPIO58
+#define APU2_LED2_L_FUNC Function1
+#define APU2_LED3_L_GPIO 0x46 // DEVSLP[1]/GPIO59
+#define APU2_LED3_L_FUNC Function3
+#define APU2_PE3_WDIS_L_GPIO 0x47 // GPIO64
+#define APU2_PE3_WDIS_L_FUNC Function2
+#define APU2_PE4_WDIS_L_GPIO 0x48 // GPIO68
+#define APU2_PE4_WDIS_L_FUNC Function0
+#define APU2_SKR_GPIO 0x5B // SPKR/GPIO66
+#define APU2_SKR_FUNC Function0
+#define APU2_PROCHOT_GPIO 0x4D // GPIO71
+#define APU2_PROCHOT_FUNC Function0
+#define APU2_BIOS_CONSOLE_GPIO 0x59 // GENINT1_L/GPIO32
+#define APU2_BIOS_CONSOLE_FUNC Function0
diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt
new file mode 100644
index 0000000..6b676ba
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/board_info.txt
@@ -0,0 +1,6 @@
+Board name: PC Engines APU2
+Board URL:
+Category: customer
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
diff --git a/src/mainboard/pcengines/apu2/cmos.default b/src/mainboard/pcengines/apu2/cmos.default
new file mode 100644
index 0000000..82fe3d2
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/cmos.default
@@ -0,0 +1,13 @@
+boot_option=Fallback
+last_boot=Fallback
+ECC_memory=Disable
+hw_scrubber=Disable
+interleave_chip_selects=Disable
+max_mem_clock=400Mhz
+multi_core=Enable
+power_on_after_fail=Disable
+slow_cpu=off
+nmi=Disable
+boot_devices='uda1'
+baud_rate=115200
+debug_level=Spew
diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout
new file mode 100644
index 0000000..1ab065d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/cmos.layout
@@ -0,0 +1,126 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+
+# SHOULD MATCH CONFIG_CMOS_SKIP_PXE_LOC 0x32 and MASK 0x2 :: ELTAN SEABIOS
+401 1 e 11 network_boot
+
+412 4 e 6 debug_level
+
+## ETHERBOOT
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+## ETHERBOOT
+
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+
+#FILO
+# coreboot config options: bootloader
+448 256 s 0 boot_devices
+#FILO
+
+728 256 h 0 user_data
+
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb
new file mode 100644
index 0000000..d6a0d13
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/devicetree.cb
@@ -0,0 +1,92 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/pi/00730F01
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 off end # IOMMU
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 off end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
+ device pci 2.2 on end # LAN3
+ device pci 2.3 on end # LAN2
+ device pci 2.4 on end # LAN1
+ device pci 2.5 on end # mPCIe slot 1
+ device pci 8.0 on end # Platform Security Processor
+ end #chip northbridge/amd/pi/00730F01
+
+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
+ device pci 11.0 on end # SATA
+ device pci 12.0 off end # USB EHCI0 usb[0:3] not connected
+ device pci 13.0 on end # USB EHCI1 usb[4:7]
+ device pci 14.0 on end # SM
+# disabled device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d # SIO NCT5104D
+ register "irq_trigger_type" = "0"
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 on
+ # UART C is conditionally turned on
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.11 on
+ # UART D is conditionally turned on
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.8 off end
+ device pnp 2e.f off end
+ # GPIO0 and GPIO1 are conditionally turned on
+ device pnp 2e.007 on end
+ device pnp 2e.107 on end
+ device pnp 2e.607 off end
+ device pnp 2e.e off end
+ end # SIO NCT5104D
+ end # LPC 0x439d
+
+ device pci 14.7 on end # SD
+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
+ end #chip southbridge/amd/pi/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
new file mode 100644
index 0000000..ad8239b
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/pi/00730F01/acpi/cpu.asl>
+
+ /* Contains the supported sleep states for this chipset */
+ #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/fch.asl>
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include "acpi/pci_int.asl"
+
+
+
+
+ } /* End \_SB scope */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c
new file mode 100644
index 0000000..3a6c87e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/irq_tables.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam16.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+#define IRQ_BITMAP 0xdee8 //0xdef8 Removed IRQ 4, this is used for serial
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, IRQ_BITMAP, 0x2, IRQ_BITMAP, 0x3, IRQ_BITMAP, 0x4, IRQ_BITMAP, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
new file mode 100644
index 0000000..432a643
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <arch/acpi.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#if CONFIG_USE_OPTION_TABLE
+#include <pc80/mc146818rtc.h>
+#endif //CONFIG_USE_OPTION_TABLE
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif //CONFIG_HAVE_OPTION_TABLE
+#include <timestamp.h>
+#include <fchgpio.h>
+#include "apu2.h"
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+#include <cbfs.h>
+#include <spd_cache.h>
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+
+static void mainboard_enable(device_t dev)
+{
+ struct device *sio_dev;
+
+ setup_bsp_ramtop();
+ u32 TOM1 = bsp_topmem() / (1024 *1024); // Tom1 in Mbyte
+ u32 TOM2 = ( bsp_topmem2() / (1024 *1024)) - 4 * 1024; // Tom2 in Mbyte
+ printk(BIOS_ERR, "%d MB", TOM1+TOM2);
+
+ u8 spd_buffer[128];
+ int index = 0;
+
+ /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/
+
+ if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0;
+ if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1;
+
+ printk(BIOS_SPEW, "Reading SPD index %d to get ECC info \n", index);
+ if (read_spd_from_cbfs(spd_buffer, index) < 0)
+ spd_buffer[3]=3; // Indicate no ECC
+
+ if ( spd_buffer[3] == 8 ) printk(BIOS_ERR, " ECC");
+ printk(BIOS_ERR, " DRAM\n\n");
+
+ //
+ // Enable the RTC output
+ //
+ pm_write16 ( 0x56, pm_read16( 0x56 ) | (1 << 11));
+
+ //
+ // Enable power on from WAKE#
+ //
+ pm_write16 ( 0xBA, pm_read16( 0xBA ) | (1 << 14));
+
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3earlyrestore();
+
+//
+// SIO CONFIG, enable and disable UARTC and UARTD depending on the selection
+//
+#if CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE
+ printk(BIOS_INFO, "UARTC enabled\n");
+
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP3);
+ if ( sio_dev ) sio_dev->enabled = 1;
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO0);
+ if ( sio_dev ) sio_dev->enabled = 0;
+
+#else //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE
+ printk(BIOS_INFO, "UARTC disabled\n");
+
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP3);
+ if ( sio_dev ) sio_dev->enabled = 0;
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO0);
+ if ( sio_dev ) sio_dev->enabled = 1;
+#endif //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTC_ENABLE
+
+
+#if CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE
+ printk(BIOS_INFO, "UARTD enabled\n");
+
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP4);
+ if ( sio_dev ) sio_dev->enabled = 1;
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO1);
+ if ( sio_dev ) sio_dev->enabled = 0;
+
+#else //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE
+ printk(BIOS_INFO, "UARTD disabled\n");
+
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_SP4);
+ if ( sio_dev ) sio_dev->enabled = 0;
+ sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO1);
+ if ( sio_dev ) sio_dev->enabled = 1;
+
+#endif //CONFIG_SUPERIO_NUVOTON_NCT5104D_UARTD_ENABLE
+}
+
+static void mainboard_final(void *chip_info) {
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER "final\n");
+
+/* Disabling LPCCLK0 which is unused according to the schematic doesn't work. The system is stuck if we do this
+ * So we don't do this.
+
+ */
+
+#if CONFIG_DUMP_GPIO_CONFIGURATION
+ //DumpGpioConfiguration( );
+#endif //CONFIG_DUMP_GPIO_CONFIGURATION
+
+#if CONFIG_DUMP_CLOCK_CONFIGURATION
+ //DumpClockConfiguration( );
+#endif //CONFIG_DUMP_GPIO_CONFIGURATION
+
+#if CONFIG_DUMP_LINK_CONFIGURATION
+ //DumpLinkConfiguration( );
+#endif //CONFIG_DUMP_LINK_CONFIGURATION
+
+ //
+ // Turn off LED 2 and 3
+ //
+ printk(BIOS_INFO, "Turn off LED 2 and 3\n");
+ WriteFchGpio( APU2_LED2_L_GPIO, 1);
+ WriteFchGpio( APU2_LED3_L_GPIO, 1);
+
+ printk(BIOS_INFO, "USB PORT ROUTING = 0x%08x\n", *((u8 *)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF )));
+ if ( *((u8 *)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF )) & (1<<7) ) {
+
+ printk(BIOS_INFO, "USB PORT ROUTING = XHCI PORTS ENABLED\n");
+ } else {
+
+ printk(BIOS_INFO, "USB PORT ROUTING = EHCI PORTS ENABLED\n");
+ }
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+ .final = mainboard_final,
+};
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
new file mode 100644
index 0000000..320e5ba
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+//#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
+#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */
+#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> // IRQ routing info
+
+
+u8 picr_data[FCH_INT_TABLE_SIZE] = {
+ 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+u8 intr_data[FCH_INT_TABLE_SIZE] = {
+ 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[PIRQ_B]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[PIRQ_C]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+// PCI_INT(0x0, 0x14, 0x0, intr_data[PIRQ_HDA]);
+
+ /* SD card */
+ PCI_INT(0x0, 0x14, 0x1, intr_data[PIRQ_SD]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[PIRQ_EHCI1]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[PIRQ_EHCI2]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[PIRQ_EHCI3]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[PIRQ_SATA]);
+
+ /* on board NIC & Slot PCIE. */
+
+
+ /* PCIe Lan*/
+// PCI_INT(0x0, 0x06, 0x0, 0x13); // No integrated LAN
+
+// /* FCH PCIe PortA */
+// PCI_INT(0x0, 0x15, 0x0, 0x10);
+// /* FCH PCIe PortB */
+// PCI_INT(0x0, 0x15, 0x1, 0x11);
+// /* FCH PCIe PortC */
+// PCI_INT(0x0, 0x15, 0x2, 0x12);
+// /* FCH PCIe PortD */
+// PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /* GPP0 */
+ PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
+ /* GPP1 */
+ PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
+ /* GPP2 */
+ PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
+ /* GPP3 */
+ PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
+ /* GPP4 */
+ PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
+
+
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
new file mode 100644
index 0000000..2dfae0e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -0,0 +1,236 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/car.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <hudson.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <fchgpio.h>
+#include "apu2.h"
+#include <build.h>
+
+//
+// GPIO Init Table
+//
+// GPIO_DEFINITION(gpio, function, outputenable, output, pullup, pulldown)
+static const GPIO_CONTROL gGpioInitTable[] = {
+ GPIO_DEFINITION (APU2_SPD_STRAP0_GPIO, APU2_SPD_STRAP0_FUNC, 0, 0, 0, 0),
+ GPIO_DEFINITION (APU2_SPD_STRAP1_GPIO, APU2_SPD_STRAP1_FUNC, 0, 0, 0, 0),
+ GPIO_DEFINITION (APU2_PE3_RST_L_GPIO, APU2_PE3_RST_L_FUNC, 1, 1, 0, 0),
+ GPIO_DEFINITION (APU2_PE4_RST_L_GPIO, APU2_PE4_RST_L_FUNC, 1, 1, 0, 0),
+ GPIO_DEFINITION (APU2_LED1_L_GPIO, APU2_LED1_L_FUNC, 1, 0, 0, 0), // Turn on the LEDs by default
+ GPIO_DEFINITION (APU2_LED2_L_GPIO, APU2_LED2_L_FUNC, 1, 0, 0, 0),
+ GPIO_DEFINITION (APU2_LED3_L_GPIO, APU2_LED3_L_FUNC, 1, 0, 0, 0),
+ GPIO_DEFINITION (APU2_PE3_WDIS_L_GPIO, APU2_PE3_WDIS_L_FUNC, 1, 1, 0, 0),
+ GPIO_DEFINITION (APU2_PE4_WDIS_L_GPIO, APU2_PE4_WDIS_L_FUNC, 1, 1, 0, 0),
+// SPKR doesn't require init, left at default
+ GPIO_DEFINITION (APU2_PROCHOT_GPIO, APU2_PROCHOT_FUNC, 0, 0, 0, 0),
+ GPIO_DEFINITION (APU2_BIOS_CONSOLE_GPIO, APU2_BIOS_CONSOLE_FUNC, 0, 0, 0, 0),
+ {0xFF, 0xFF, 0xFF} // Terminator
+ };
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+#if CONFIG_SVI2_SLOW_SPEED
+ device_t d18f3_dev = PCI_DEV(0, 0x18, 3);
+#endif //CONFIG_SVI2_SLOW_SPEED
+#if CONFIG_SVI_WAIT_COMP_DIS
+ device_t d18f5_dev = PCI_DEV(0, 0x18, 5);
+#endif //CONFIG_SVI_WAIT_COMP_DIS
+
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+
+ u32 data, *memptr;
+
+ hudson_lpc_port80();
+ //
+ // Configure the GPIO's
+ //
+ HandleFchGpioTbl ( (GPIO_CONTROL *) &gGpioInitTable[0] );
+
+ hudson_clk_output_48Mhz();
+
+ post_code(0x31);
+ console_init();
+
+ printk(BIOS_INFO, "14-25-48Mhz Clock settings\n");
+
+ memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28 );
+ data = *memptr;
+ printk(BIOS_INFO, "FCH_MISC_REG28 is 0x%08x \n", data);
+
+ memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
+ data = *memptr;
+ printk(BIOS_INFO, "FCH_MISC_REG40 is 0x%08x \n", data);
+
+ //
+ // Configure clock request
+ //
+ data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00));
+
+ data &= 0xFFFF0000;
+ data |= (0 + 1) << (0 * 4); // CLKREQ 0 to CLK0
+ data |= (1 + 1) << (1 * 4); // CLKREQ 1 to CLK1
+ data |= (2 + 1) << (2 * 4); // CLKREQ 2 to CLK2
+ data |= (3 + 1) << (3 * 4); // CLKREQ 3 to CLK3
+
+ *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00)) = data;
+
+ data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04));
+
+ data &= 0xFFFFFF0F;
+ data |= 0xA << (1 * 4); // CLKREQ GFX to GFXCLK
+
+ *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)) = data;
+
+// //
+// // Configure clock strength
+// //
+// data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24));
+//
+// data &= ~( (3 << 18) | (3 << 6) | (3 << 4) | (3 << 2) | (3 << 0) );
+// data |= 3 << 18; // GFX CLOCK
+// data |= 3 << (0 * 2); // CLK0
+// data |= 3 << (1 * 2); // CLK1
+// data |= 3 << (2 * 2); // CLK2
+// data |= 3 << (3 * 2); // CLK3
+//
+// *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)) = data;
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ /*
+ * This refers to LpcClkDrvSth settling time. Without this setting, processor
+ * initialization is slow or incorrect, so this wait has been replicated from
+ * earlier development boards.
+ */
+ { int i; for(i = 0; i < 200000; i++) inb(0xCD6); }
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ /* TODO There is no debug output between the return from amdinitreset and amdinitearly */
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
+
+ post_code(0x39);
+ agesawrapper_amdinitearly();
+
+ /*
+ // Moved here to prevent double signon message
+ // amdinitreset AGESA code might issue a reset when the hardware is in a wrong state.
+ */
+
+#if CONFIG_SVI2_SLOW_SPEED
+ /* Force SVI2 to slow speed for APU2 */
+ val = pci_read_config32( d18f3_dev, 0xA0);
+ if ( val & (1 << 14 ) ) {
+
+ printk(BIOS_DEBUG, "SVI2 FREQUENCY 20 Mhz changing to 3.4\n");
+ val &= ~(1 << 14 );
+ pci_write_config32(d18f3_dev, 0xA0, val );
+
+ } else {
+
+ printk(BIOS_DEBUG, "SVI2 FREQUENCY 3.4 Mhz\n");
+ }
+#endif //CONFIG_SVI2_SLOW_SPEED
+
+#if CONFIG_SVI_WAIT_COMP_DIS
+ /* Disable SVI2 controller to wait for command completion */
+ val = pci_read_config32( d18f5_dev, 0x12C);
+ if ( val & (1 << 30 ) ) {
+
+ printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n");
+
+ } else {
+
+ printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n");
+ val |= (1 << 30 );
+ pci_write_config32(d18f5_dev, 0x12C, val );
+ }
+
+#endif //CONFIG_SVI_WAIT_COMP_DIS
+
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
+
+ } else { /* S3 detect */
+
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ outb(0xEA, 0xCD6);
+ outb(0x1, 0xcd7);
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex
new file mode 100644
index 0000000..7fa5757
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex
@@ -0,0 +1,263 @@
+# PCEngines 2Gb 1333
+
+# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision
+# 0x13 = Revision 1.3
+13
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+03
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6.0ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+00 05
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - OEM specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+15
+
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+b6 73
diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex
new file mode 100644
index 0000000..b9d3983
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex
@@ -0,0 +1,257 @@
+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
+
+# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision -
+# 0x13 = Revision 1.3
+13
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+08
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+21
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5 ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+20 08
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+15 44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+67 94
diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex
new file mode 100644
index 0000000..7daa938
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-NOECC.spd.hex
@@ -0,0 +1,258 @@
+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
+
+# SPD contents for APU 4GB DDR3 NO ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision -
+# 0x13 = Revision 1.3
+13
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+21
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5 ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+20 08
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+15 44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+09 ff
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 5b5c851..e845689 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -39,12 +39,14 @@ ramstage-y += hda.c
ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sd.c
+ramstage-y += fchgpio.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
+romstage-y += fchgpio.c
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
romstage-y += imc.c
ramstage-y += imc.c
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index f4fcf8b..512ba22 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -25,12 +25,14 @@
#include <cbmem.h>
#include "hudson.h"
#include "pci_devs.h"
+#include <Fch/Fch.h>
+
+#define BIT2 0x0000000000000004ull
#if IS_ENABLED(CONFIG_HUDSON_UART)
#include <cpu/x86/msr.h>
#include <delay.h>
-#include <Fch/Fch.h>
void configure_hudson_uart(void)
{
@@ -121,6 +123,18 @@ void hudson_lpc_port80(void)
pci_write_config8(dev, 0x4a, byte);
}
+void hudson_clk_output_48Mhz(void)
+{
+ u32 data, *memptr;
+
+ // Enable the X14M_25M_48M_OSC pin and leaving it at it's default so 48Mhz will be on ball AP13 (FT3b package)
+
+ memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
+ data = *memptr;
+ data &= (u32)~BIT2; // clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock
+ *memptr = data;
+}
+
void hudson_lpc_decode(void)
{
device_t dev;
diff --git a/src/southbridge/amd/pi/hudson/fchgpio.c b/src/southbridge/amd/pi/hudson/fchgpio.c
new file mode 100644
index 0000000..df3a04f
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/fchgpio.c
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include "hudson.h"
+#include "fchgpio.h"
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchGpioTbl - FCH Gpio table (8 bits data)
+ *
+ * @param[in] pGpioTbl - Table data pointer, this table should be terminated by a 0xFF byte
+ *
+ */
+void
+HandleFchGpioTbl (
+ GPIO_CONTROL *pGpioTbl
+ )
+{
+ if (pGpioTbl != NULL) {
+
+ while (pGpioTbl->GpioPin != 0xFF) {
+
+ ConfigureFchGpio( pGpioTbl->GpioPin, pGpioTbl->PinFunction, pGpioTbl->CfgByte );
+ pGpioTbl++;
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ConfigureFchGpio - FCH Gpio table (8 bits data)
+ *
+ * @param[in] pGpioTbl - Table data pointer, this table should be terminated by a 0xFF byte
+ *
+ */
+void ConfigureFchGpio(u8 gpio, u8 iomux_ftn, u8 setting)
+{
+ if ( gpio <= MAX_GPIO ) { // Simply ignore invalid GPIO
+
+ u8 bdata;
+ u8 *memptr;
+
+ //
+ // First we prepare the GPIO setting and then we switch the MUX to the correct setting to prevent glitches
+ //
+
+ // The GPIO register is 4 bytes. We use bit 16 to 23 for the actual GPIO function
+ memptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + (gpio << 2) + 2 );
+ bdata = *memptr;
+ bdata |= (setting & FCH_GPIO_OUTPUT_VALUE);
+ *memptr = bdata; // First write out the data value to prevent glitches
+
+ bdata |= (setting & FCH_GPIO_ALL_CONFIG); /* set direction and data value */
+ *memptr = bdata;
+
+ memptr = (u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + gpio);
+ *memptr = iomux_ftn;
+
+ }
+}
+
+u8 ReadFchGpio(u8 gpio)
+{
+ if ( gpio <= MAX_GPIO ) {
+
+ u8 *memptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + (gpio << 2) + 2 );
+ return (*memptr & FCH_GPIO_PIN_STS) ? 1 : 0;
+
+ } else {
+
+ return GPIO_INVALID; // Indicate an invalid GPIO was requested
+ }
+}
+
+void WriteFchGpio( u8 gpio, u8 value)
+{
+ if ( gpio <= MAX_GPIO ) { // Simply ignore invalid GPIO
+
+ u8 bdata;
+ u8 *memptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + (gpio << 2) + 2 );
+ bdata = *memptr;
+ bdata &= ~FCH_GPIO_OUTPUT_VALUE;
+ if ( value ) bdata |= FCH_GPIO_OUTPUT_VALUE;
+ *memptr = bdata;
+ }
+}
+
+void DumpGpioConfiguration( void )
+{
+ int i;
+
+ printk(BIOS_INFO, "GPIO Bank 0 Control Registers\n");
+
+ for ( i = 0 ; i <= 0xf8 ; i = i + 4 ) {
+
+ printk(BIOS_INFO, "GPIOx%03x = 0x%08x \n", i, *((u32 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + i )));
+ }
+
+ printk(BIOS_INFO, "GPIO Bank 1 Control Registers\n");
+
+ for ( i = 0x100 ; i <= 0x1fc ; i = i + 4 ) {
+
+ printk(BIOS_INFO, "GPIOx%03x = 0x%08x \n", i, *((u32 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + i )));
+ }
+
+ printk(BIOS_INFO, "GPIO Bank 2 Control Registers\n");
+
+ for ( i = 0x200 ; i <= 0x2dc ; i = i + 4 ) {
+
+ printk(BIOS_INFO, "GPIOx%03x = 0x%08x \n", i, *((u32 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE + i )));
+ }
+
+ printk(BIOS_INFO, "GPIO MUX Registers\n");
+
+ for ( i = 0x00 ; i <= 0x26 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x40 ; i <= 0x49 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x4C ; i <= 0x4D ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x54 ; i <= 0x55 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x57 ; i <= 0x65 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x71 ; i <= 0x74 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x7E ; i <= 0x7E ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+ for ( i = 0x81 ; i <= 0x84 ; i++ ) printk(BIOS_INFO, "IOMUXx%02x = %d\n", i, *((u8 *)(ACPI_MMIO_BASE + IOMUX_BASE + i )));
+}
diff --git a/src/southbridge/amd/pi/hudson/fchgpio.h b/src/southbridge/amd/pi/hudson/fchgpio.h
new file mode 100644
index 0000000..717f5e5
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/fchgpio.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+
+ *
+ * Copyright (C) 2015 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <agesawrapper.h>
+#include "FchPlatform.h"
+
+#define GPIO_DEFINITION(gpio, function, outputenable, output, pullup, pulldown) \
+{gpio, function, (outputenable << 7) | (output << 6) | (pullup << 4) | (pulldown << 5) }
+
+void HandleFchGpioTbl ( GPIO_CONTROL *pGpioTbl );
+void ConfigureFchGpio(u8 gpio, u8 iomux_ftn, u8 setting);
+u8 ReadFchGpio(u8 gpio);
+void WriteFchGpio(u8 gpio, u8 setting);
+void DumpGpioConfiguration( void );
+
+#define GPIO_DATA_LOW 0
+#define GPIO_DATA_HIGH 1
+#define GPIO_INVALID 0xFF
+
+#define MAX_GPIO 183 // Maximum GPIO supported
+
+//
+// FCH MMIO Base (GPIO BANK0)
+// offset : 0x1500
+//
+#define FCH_GPIO_PIN_STS BIT0 // Bit 16
+#define FCH_GPIO_PULL_UP_ENABLE BIT4 // Bit 20
+#define FCH_GPIO_PULL_DOWN_ENABLE BIT5 // Bit 21
+#define FCH_GPIO_OUTPUT_VALUE BIT6 // Bit 22
+//#define FCH_GPIO_OUTPUT_ENABLE BIT7 // Bit 23
+#define FCH_GPIO_ALL_CONFIG (FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_PULL_DOWN_ENABLE |FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE)
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