[coreboot-gerrit] New patch to review for coreboot: mainboard/asus: Add F2A85-M PRO variant to F2A85-M.
Denis Carikli (GNUtoo@no-log.org)
gerrit at coreboot.org
Fri Oct 7 18:52:26 CEST 2016
Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16931
-gerrit
commit 0b359b14331e7fc4acf033fba0b6cc0d6689b4d6
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date: Sun Jul 26 19:57:51 2015 +0200
mainboard/asus: Add F2A85-M PRO variant to F2A85-M.
Status:
- Serial works:
Serial logs appear, starting from the romstage
- The primary PCIe 16x slot works
It was tested with a GPU compatible with nouveau
- USB and audio are not very reliable
- The ethernet card is not seen with lspci
- The secondary pcie16x slot isn't working:
When plugging a GPU inside, it's not seen with lspci
- SATA works:
The board fully boots GNU/Linux.
Note that when running the shutdown command, the default
boot firmware will rewrite part of the boot flash before
powering off the machine.
Flashing coreboot internally from the default boot fimrware can
still work, if the power plug is removed after running flashrom.
Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c | 1 +
src/mainboard/asus/f2a85-m_pro/Kconfig | 97 ++++++++
src/mainboard/asus/f2a85-m_pro/Kconfig.name | 2 +
src/mainboard/asus/f2a85-m_pro/Makefile.inc | 22 ++
src/mainboard/asus/f2a85-m_pro/OemCustomize.c | 27 +++
src/mainboard/asus/f2a85-m_pro/OptionsIds.h | 0
.../asus/f2a85-m_pro/PlatformGnbPcieComplex.h | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/routing.asl | 255 +++++++++++++++++++++
src/mainboard/asus/f2a85-m_pro/acpi/sata.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/si.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/superio.asl | 16 ++
src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi_tables.c | 1 +
src/mainboard/asus/f2a85-m_pro/board_info.txt | 7 +
src/mainboard/asus/f2a85-m_pro/buildOpts.c | 1 +
src/mainboard/asus/f2a85-m_pro/cmos.layout | 74 ++++++
src/mainboard/asus/f2a85-m_pro/devicetree.cb | 172 ++++++++++++++
src/mainboard/asus/f2a85-m_pro/dsdt.asl | 1 +
src/mainboard/asus/f2a85-m_pro/irq_tables.c | 1 +
src/mainboard/asus/f2a85-m_pro/mainboard.c | 1 +
src/mainboard/asus/f2a85-m_pro/mptable.c | 1 +
src/mainboard/asus/f2a85-m_pro/romstage.c | 150 ++++++++++++
28 files changed, 839 insertions(+)
diff --git a/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c b/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c
new file mode 100644
index 0000000..afa69bb
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c
@@ -0,0 +1 @@
+#include "../f2a85-m/BiosCallOuts.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig b/src/mainboard/asus/f2a85-m_pro/Kconfig
new file mode 100644
index 0000000..b95f42f
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/Kconfig
@@ -0,0 +1,97 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_F2A85_M_PRO
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select SUPERIO_NUVOTON_NCT6779D
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+ select HUDSON_DISABLE_IMC
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150
+
+config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/f2a85-m_pro
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "F2A85-M_PRO"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,9993"
+
+endif # BOARD_ASUS_F2A85_M_PRO
diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig.name b/src/mainboard/asus/f2a85-m_pro/Kconfig.name
new file mode 100644
index 0000000..e4b8dfd
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_F2A85_M_PRO
+ bool "F2A85-M PRO"
diff --git a/src/mainboard/asus/f2a85-m_pro/Makefile.inc b/src/mainboard/asus/f2a85-m_pro/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/f2a85-m_pro/OemCustomize.c b/src/mainboard/asus/f2a85-m_pro/OemCustomize.c
new file mode 100644
index 0000000..77566f4
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/OemCustomize.c
@@ -0,0 +1,27 @@
+#include "../f2a85-m/OemCustomize.c"
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+/*
+ TODO: is this OK for DDR3 socket FM2?
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ */
+ PSO_END
+};
+#endif /* CONFIG_BOARD_ASUS_F2A85M_PRO */
diff --git a/src/mainboard/asus/f2a85-m_pro/OptionsIds.h b/src/mainboard/asus/f2a85-m_pro/OptionsIds.h
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..f6f4c9a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h
@@ -0,0 +1 @@
+#include "../f2a85-m/PlatformGnbPcieComplex.h"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl b/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl
new file mode 100644
index 0000000..43c2428
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/AmdImc.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl
new file mode 100644
index 0000000..29c8d69
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/cpstate.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl b/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl
new file mode 100644
index 0000000..4794311
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/gpe.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl
new file mode 100644
index 0000000..f81742e
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/mainboard.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl b/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl
new file mode 100644
index 0000000..4d6d511
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl
@@ -0,0 +1,255 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ Package(){0x000FFFFF, 0, INTA, 0 },
+ Package(){0x000FFFFF, 1, INTB, 0 },
+ Package(){0x000FFFFF, 2, INTC, 0 },
+ Package(){0x000FFFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl b/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl
new file mode 100644
index 0000000..46bc2e6
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/sata.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/si.asl b/src/mainboard/asus/f2a85-m_pro/acpi/si.asl
new file mode 100644
index 0000000..208e5c4
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/si.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/si.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl b/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl
new file mode 100644
index 0000000..67e4e2b
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/sleep.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl b/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl
new file mode 100644
index 0000000..6f95a8a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl b/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl
new file mode 100644
index 0000000..3d529e5
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/thermal.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl
new file mode 100644
index 0000000..1b3fba0
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl
@@ -0,0 +1 @@
+include "../../f2a85-m/acpi/usb_oc.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi_tables.c b/src/mainboard/asus/f2a85-m_pro/acpi_tables.c
new file mode 100644
index 0000000..febb723
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi_tables.c
@@ -0,0 +1 @@
+#include "../f2a85-m/acpi_tables.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/board_info.txt b/src/mainboard/asus/f2a85-m_pro/board_info.txt
new file mode 100644
index 0000000..52c5819
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: http://www.asus.com/Motherboards/F2A85M_PRO/
+ROM package: DIP8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year:
diff --git a/src/mainboard/asus/f2a85-m_pro/buildOpts.c b/src/mainboard/asus/f2a85-m_pro/buildOpts.c
new file mode 100644
index 0000000..c9fc086
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/buildOpts.c
@@ -0,0 +1 @@
+#include "../f2a85-m/buildOpts.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/cmos.layout b/src/mainboard/asus/f2a85-m_pro/cmos.layout
new file mode 100644
index 0000000..75a2d30
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/cmos.layout
@@ -0,0 +1,74 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/f2a85-m_pro/devicetree.cb b/src/mainboard/asus/f2a85-m_pro/devicetree.cb
new file mode 100644
index 0000000..238ab51
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/devicetree.cb
@@ -0,0 +1,172 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 2.0 on end # Internal Graphics P2P bridge 0x99XX
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 52 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 2
+ device i2c 51 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 3
+ device i2c 53 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # unused
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x780e
+ chip superio/nuvoton/nct5572d
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 off end # LPT1
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2/IR
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on # GPIO6, GPIO7, GPIO8
+ io 0xe0 = 0x7f
+ io 0xe1 = 0x10
+ io 0xe2 = 0x00
+ io 0xe3 = 0x00
+ io 0xe4 = 0xff
+ io 0xe5 = 0xff
+ io 0xe6 = 0xff
+ io 0xe7 = 0xff
+ io 0xec = 0x00
+ io 0xed = 0xff
+ io 0xf4 = 0xff
+ io 0xf5 = 0xff
+ io 0xf6 = 0x00
+ io 0xf7 = 0x00
+ io 0xf8 = 0x00
+ end
+ device pnp 2e.8 on # WDT1, GPIO0, GPIO1
+ io 0x30 = 0x00
+ io 0x60 = 0x00
+ io 0x61 = 0x00
+ io 0xe0 = 0xff
+ io 0xe1 = 0xff
+ io 0xe2 = 0xff
+ io 0xe3 = 0xff
+ io 0xe4 = 0xff
+ io 0xf0 = 0xff
+ io 0xf1 = 0x28
+ io 0xf2 = 0x00
+ io 0xf3 = 0x00
+ io 0xf4 = 0x08
+ io 0xf5 = 0xff
+ io 0xf6 = 0x00
+ io 0xf7 = 0xff
+ end
+ device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8
+ io 0x30 = 0xfe
+ io 0xe0 = 0xff
+ io 0xe1 = 0x90
+ io 0xe2 = 0x00
+ io 0xe3 = 0x00
+ io 0xe4 = 0x7f
+ io 0xe5 = 0x76
+ io 0xe6 = 0x00
+ io 0xe7 = 0x00
+ io 0xe8 = 0x00
+ io 0xe9 = 0x00
+ io 0xea = 0x00
+ io 0xeb = 0x00
+ io 0xee = 0x00
+ io 0xf0 = 0xff
+ io 0xf1 = 0x7b
+ io 0xf2 = 0x00
+ io 0xf4 = 0xff
+ io 0xf5 = 0xef
+ io 0xf6 = 0x00
+ io 0xf7 = 0x00
+ io 0xfe = 0x00
+ end
+ device pnp 2e.a on # ACPI
+ io 0xe6 = 0x4c
+ io 0xe7 = 0x11
+ io 0xf2 = 0x5d
+ end
+ device pnp 2e.b on # Hardware Monitor, Front Panel LED
+ io 0x30 = 0x01
+ io 0x60 = 0x02
+ io 0x61 = 0x90
+ io 0xe2 = 0x7f
+ io 0xe4 = 0xf1
+ end
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off # GPIO Push-pull/Open-drain selection
+ io 0xe6 = 7f
+ end
+ device pnp 2e.14 off # PORT80 UART
+ io 0xe0 = 0x00
+ end
+ device pnp 2e.16 off end # Deep Sleep
+ end
+ end #device pci 14.3 # LPC
+
+ device pci 14.4 on end # PCI bridge
+ device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806])
+ device pci 15.0 on end # PCI bridge
+ device pci 15.1 on end # PCI bridge
+ device pci 15.2 on end # PCI bridge # Only present with the original boot firmware
+ end #chip southbridge/amd/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m_pro/dsdt.asl b/src/mainboard/asus/f2a85-m_pro/dsdt.asl
new file mode 100644
index 0000000..b27b81d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/dsdt.asl
@@ -0,0 +1 @@
+#include "../f2a85-m/dsdt.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/irq_tables.c b/src/mainboard/asus/f2a85-m_pro/irq_tables.c
new file mode 100644
index 0000000..7e6c693
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/irq_tables.c
@@ -0,0 +1 @@
+#include "../f2a85-m/irq_tables.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/mainboard.c b/src/mainboard/asus/f2a85-m_pro/mainboard.c
new file mode 100644
index 0000000..d8cc9c8
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/mainboard.c
@@ -0,0 +1 @@
+#include "../f2a85-m/mainboard.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/mptable.c b/src/mainboard/asus/f2a85-m_pro/mptable.c
new file mode 100644
index 0000000..1d0784d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/mptable.c
@@ -0,0 +1 @@
+#include <mainboard/asus/f2a85-m/mptable.c>
diff --git a/src/mainboard/asus/f2a85-m_pro/romstage.c b/src/mainboard/asus/f2a85-m_pro/romstage.c
new file mode 100644
index 0000000..cbe4328
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/romstage.c
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/amd/car.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pnp_def.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+#include <stdint.h>
+#include <string.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO 0xFED80000
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+ u8 byte;
+ pci_devfn_t dev;
+
+#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
+ hudson_pci_port80();
+#endif
+#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
+ hudson_lpc_port80();
+#endif
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+ post_code(0x39);
+
+ agesawrapper_amdinitearly();
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+ amd_initcpuio();
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
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