[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 20:48:46 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16967
-gerrit
commit 022e129269c006857f700e2977d4ffeffd158c83
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 20:32:25 2016 +0200
mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented code
Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 55 +++++++------
src/mainboard/amd/db-ft3b-lc/OemCustomize.c | 120 ++++++++++++++--------------
src/mainboard/amd/db-ft3b-lc/romstage.c | 1 -
3 files changed, 87 insertions(+), 89 deletions(-)
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index a62c0be..63b14ac 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -140,7 +140,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
};
- LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
+ LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
/* Enable IMC fan control. the recommended way */
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
@@ -158,8 +158,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* Thermal Zone Parameter */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; //6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /* BIT0 | BIT2 | BIT5 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; /* 6 | BIT3 */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
@@ -170,15 +170,15 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* IMC Fan Policy temperature thresholds */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /* AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /* AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /* AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
/* IMC Fan Policy PWM Settings */
@@ -195,7 +195,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
@@ -205,20 +205,20 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /* AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /* AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /* AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */
FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /* Zone */
FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
@@ -230,7 +230,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
@@ -241,7 +241,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
@@ -251,7 +251,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
/* IMC Function */
- FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8;
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /*BIT0 | BIT4 |BIT8; */
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
@@ -279,7 +279,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
index e8146a0..bffe888 100644
--- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
+++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
@@ -118,66 +118,66 @@ OemCustomizeInitEarly (
* use its default conservative settings.
*/
static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
+ /*
+ * The following macros are supported (use comma to separate macros):
+ *
+ * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ * The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ * AGESA will base on this value to disable unused MemClk to save power.
+ * Example:
+ * BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ * Bit AM3/S1g3 pin name
+ * 0 M[B,A]_CLK_H/L[0]
+ * 1 M[B,A]_CLK_H/L[1]
+ * 2 M[B,A]_CLK_H/L[2]
+ * 3 M[B,A]_CLK_H/L[3]
+ * 4 M[B,A]_CLK_H/L[4]
+ * 5 M[B,A]_CLK_H/L[5]
+ * 6 M[B,A]_CLK_H/L[6]
+ * 7 M[B,A]_CLK_H/L[7]
+ * And platform has the following routing:
+ * CS0 M[B,A]_CLK_H/L[4]
+ * CS1 M[B,A]_CLK_H/L[2]
+ * CS2 M[B,A]_CLK_H/L[3]
+ * CS3 M[B,A]_CLK_H/L[5]
+ * Then platform can specify the following macro:
+ * MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ *
+ * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ * The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ * AGESA will base on this value to tristate unused CKE to save power.
+ *
+ * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ * The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ * AGESA will base on this value to tristate unused ODT pins to save power.
+ *
+ * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ * The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ * AGESA will base on this value to tristate unused Chip select to save power.
+ *
+ * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ * Specifies the number of DIMM slots per channel.
+ *
+ * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ * Specifies the number of Chip selects per channel.
+ *
+ * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ * Specifies the number of channels per socket.
+ *
+ * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ * Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ *
+ * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ * Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ *
+ * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ * Byte6Seed, Byte7Seed, ByteEccSeed)
+ * Specifies the write leveling seed for a channel of a socket.
+ *
+ * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ * Byte6Seed, Byte7Seed, ByteEccSeed)
+ * Speicifes the HW RXEN training seed for a channel of a socket
+ */
#define SEED_WL 0x0E
WRITE_LEVELING_SEED(
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index f69e188..5c7796f 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -81,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
- //PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
/*
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