[coreboot-gerrit] Patch set updated for coreboot: lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O reads

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14801

-gerrit

commit e573e77f1ed7efd445e6c480623b977da22b659f
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Thu May 19 16:02:38 2016 +0200

    lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O reads
    
    Requesting low power acpi cpu c-states has two software interfaces:
    Using P_LVLx I/O reads or using equivalent MWAIT requests.
    This change makes it more consistent with newer targets that use MWAIT
    requests.
    
    There also exists extended intel acpi c-states which can be enabled
    in two ways:
    - using a substate hint to the mwait request (defined in bios);
    - setting a model specific register (msr)
    
    Currently this is done by setting the right msr bits but with this
    change one can experiment by adding substate hints.
    
    Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/mainboard/lenovo/x60/mainboard.c | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index 5ea4221..b1096d2 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -38,10 +38,37 @@
 
 #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
 
+#define MWAIT_RES(state, sub_state)                         \
+	{						    \
+		.space_id = ACPI_ADDRESS_SPACE_FIXED,	    \
+		.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
+		.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
+		{					    \
+			.resv = 0,			    \
+		},					    \
+		.addrl = (((state) << 4) | (sub_state)),    \
+		.addrh = 0,				    \
+			 }
+
 static acpi_cstate_t cst_entries[] = {
-	{ 1,  1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
-	{ 2,  1,  500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
-	{ 2, 17,  250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
+	{
+		.ctype = 1,
+		.latency = 1,
+		.power = 1000,
+		.resource = MWAIT_RES(0, 0),
+	},
+	{
+		.ctype = 2,
+		.latency = 1,
+		.power = 500,
+		.resource = MWAIT_RES(1, 0),
+	},
+	{
+		.ctype = 3,
+		.latency = 17,
+		.power = 250,
+		.resource = MWAIT_RES(2, 0),
+	},
 };
 
 int get_cst_entries(acpi_cstate_t **entries)