[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/inagua: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 20:56:01 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16969
-gerrit
commit 704e1a1d7f7522c09069b6a75b086a61266b5629
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 20:54:12 2016 +0200
mainboard/amd/inagua: Use C89 comments style & remove commented code
Change-Id: Ie4f64c83cb42725afc2202863c8859139bdb41d3
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/inagua/BiosCallOuts.c | 26 +--
src/mainboard/amd/inagua/OemCustomize.c | 19 +--
src/mainboard/amd/inagua/OptionsIds.h | 8 -
src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 82 ++++-----
src/mainboard/amd/inagua/broadcom.c | 197 +++++++++++-----------
src/mainboard/amd/inagua/mptable.c | 2 +-
src/mainboard/amd/inagua/platform_cfg.h | 2 +-
7 files changed, 163 insertions(+), 173 deletions(-)
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 5d11c06..4c64b47 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
- // Get SB800 MMIO Base (AcpiMmioAddr)
+ /* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
@@ -151,14 +151,14 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */
Status = AGESA_SUCCESS;
break;
}
@@ -167,14 +167,14 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */
Status = AGESA_SUCCESS;
break;
}
@@ -183,14 +183,14 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */
Status = AGESA_SUCCESS;
break;
}
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
index d1f715c..8bcf666 100644
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -48,25 +48,25 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = {
- // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
+ /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
},
- // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
+ /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
},
- // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
+ /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
},
- // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
@@ -75,13 +75,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
- // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
+ /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
},
- // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
+ /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
@@ -96,11 +96,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
&DdiList[0]
};
- // GNB PCIe topology Porting
+ /* GNB PCIe topology Porting */
+
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
- //
- // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
- //
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h
index 2d8381b..7a9c03f 100644
--- a/src/mainboard/amd/inagua/OptionsIds.h
+++ b/src/mainboard/amd/inagua/OptionsIds.h
@@ -43,14 +43,6 @@
**/
#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
-
#endif
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
index 60045e1..fd92667 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -20,44 +20,44 @@
#include "AGESA.h"
#include "amdlib.h"
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
+/* GNB GPP Port4 */
+#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
+
+/* GNB GPP Port5 */
+#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
+
+/* GNB GPP Port6 */
+#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
+
+/* GNB GPP Port7 */
+#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
+
+/* GNB GPP Port8 */
+#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
+
+#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c
index 640f639..92b5931 100644
--- a/src/mainboard/amd/inagua/broadcom.c
+++ b/src/mainboard/amd/inagua/broadcom.c
@@ -26,28 +26,28 @@
#include <types.h>
#include <console/console.h>
-#include <device/device.h> //Coreboot device access
+#include <device/device.h> /* Coreboot device access */
#include <device/pci.h>
#include <delay.h>
#include <endian.h>
void broadcom_init(void);
-#define be16(x) cpu_to_be16(x) //a little easier to type
-#define be(x) cpu_to_be32(x) //this is used a lot!
+#define be16(x) cpu_to_be16(x) /* a little easier to type */
+#define be(x) cpu_to_be32(x) /* this is used a lot! */
/* C forces us to specify these before defining struct selfboot_patch :-( */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
#define INIT1_LENGTH 9
#define INIT2_LENGTH 10
#define INIT3_LENGTH 3
-#define INIT4_LENGTH 7 //this one may be 0
+#define INIT4_LENGTH 7 /* this one may be 0 */
#define PWRDN_LENGTH 5
#else
#define INIT1_LENGTH 13
#define INIT2_LENGTH 6
#define INIT3_LENGTH 3
-#define INIT4_LENGTH 11 //this one may be 0
+#define INIT4_LENGTH 11 /* this one may be 0 */
#define PWRDN_LENGTH 4
#endif
@@ -106,61 +106,61 @@ void broadcom_init(void);
* not supported.
*/
-static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
+static struct selfboot_patch { /* Watch out: all values are *BIG-ENDIAN*! */
struct { /* Global header */
- u8 signature; //0xA5
- u8 format; //bits 7-3: patch format; 2-0: revision
+ u8 signature; /* 0xA5 */
+ u8 format; /* bits 7-3: patch format; 2-0: revision */
u8 mac_addr[6];
- u16 subsys_device; //IDs will be loaded into PCI config space
+ u16 subsys_device; /* IDs will be loaded into PCI config space */
u16 subsys_vendor;
- u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4)
- u8 unknown1[8]; //?, noticed no effect
- u16 basic_config; //?, see below
- u8 checksum; //byte sum of header == 0
- u8 unknown2; //?, patch rejected if changed
- u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...)
+ u16 pci_device; /* PCI device ID; vendor is always Broadcom (0x14E4) */
+ u8 unknown1[8]; /* ?, noticed no effect */
+ u16 basic_config; /* ?, see below */
+ u8 checksum; /* byte sum of header == 0 */
+ u8 unknown2; /* ?, patch rejected if changed */
+ u16 patch_version; /* 10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) */
} header;
struct { /* Init code */
- u8 checksum; //byte sum of init == 0
- u8 unknown; //?, looks unused
- u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported
- u8 size; //total size of all hunk#_code[] in bytes
- u8 hunk1_when; //mark when hunk1_code gets executed
- u8 hunk1_size; //sizeof(hunk1_code)
+ u8 checksum; /* byte sum of init == 0 */
+ u8 unknown; /* ?, looks unused */
+ u8 num_hunks; /* 0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported */
+ u8 size; /* total size of all hunk#_code[] in bytes */
+ u8 hunk1_when; /* mark when hunk1_code gets executed */
+ u8 hunk1_size; /* sizeof(hunk1_code) */
u8 hunk2_when;
u8 hunk2_size;
u8 hunk3_when;
u8 hunk3_size;
- u8 hunk4_when; //0x00 (padding) if only 3 hunks
- u8 hunk4_size; //dito
- u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below
+ u8 hunk4_when; /* 0x00 (padding) if only 3 hunks */
+ u8 hunk4_size; /* dito */
+ u32 hunk1_code[INIT1_LENGTH]; /* actual commands, see below */
u32 hunk2_code[INIT2_LENGTH];
u32 hunk3_code[INIT3_LENGTH];
- u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks
+ u32 hunk4_code[INIT4_LENGTH]; /* missing (zero length) if only 3 hunks */
} init;
struct { /* Power down code */
- u8 checksum; //byte sum of powerdown == 0
- u8 unknown; //?, looks unused
- u8 num_hunks; //0x20 = 1 hunk, other values not supported
- u8 size; //total size of all hunk#_code[] in bytes
- u8 hunk1_when; //mark when hunk1_code gets executed
- u8 hunk1_size; //sizeof(hunk1_code)
- u16 padding; //0x0000, hunk2 is not supported
- u32 hunk1_code[PWRDN_LENGTH]; //commands, see below
+ u8 checksum; /* byte sum of powerdown == 0 */
+ u8 unknown; /* ?, looks unused */
+ u8 num_hunks; /* 0x20 = 1 hunk, other values not supported */
+ u8 size; /* total size of all hunk#_code[] in bytes */
+ u8 hunk1_when; /* mark when hunk1_code gets executed */
+ u8 hunk1_size; /* sizeof(hunk1_code) */
+ u16 padding; /* 0x0000, hunk2 is not supported */
+ u32 hunk1_code[PWRDN_LENGTH]; /* commands, see below */
} powerdown;
} selfboot_patch = {
/* Keep the following invariant for valid Selfboot patches */
.header.signature = 0xA5,
- .header.format = 0x23, //format 1 revision 3
+ .header.format = 0x23, /* format 1 revision 3 */
.header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .header.checksum = 0, //calculated later
+ .header.checksum = 0, /* calculated later */
.header.unknown2 = 0x30,
- .init.checksum = 0, //calculated later
+ .init.checksum = 0, /* calculated later */
.init.unknown = 0x00,
.init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60,
.init.size = sizeof(selfboot_patch.init.hunk1_code)
@@ -171,7 +171,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
.init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code),
.init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code),
.init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code),
- .powerdown.checksum = 0, //calculated later
+ .powerdown.checksum = 0, /* calculated later */
.powerdown.unknown = 0x00,
.powerdown.num_hunks = 0x20,
.powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code),
@@ -180,19 +180,19 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
/* Only the lines below may be adapted to your needs ... */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom
- .header.subsys_device = be16(0x1699), //same as pci_device
- .header.subsys_vendor = be16(0x14E4), //Broadcom
+ .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, /* Broadcom */
+ .header.subsys_device = be16(0x1699), /* same as pci_device */
+ .header.subsys_vendor = be16(0x14E4), /* Broadcom */
#else
- .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT
- .header.subsys_device = be16(0x1699), //simply kept this
- .header.subsys_vendor = be16(0x121D), //LiPPERT
+ .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, /* LiPPERT */
+ .header.subsys_device = be16(0x1699), /* simply kept this */
+ .header.subsys_vendor = be16(0x121D), /* LiPPERT */
#endif
- .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY
+ .header.pci_device = be16(0x1699), /* Broadcom 5785 with GbE PHY */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11)
+ .header.patch_version = be16(0x010B), /* 1.11 (Broadcom's sb5785m1.11) */
#else
- .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-)
+ .header.patch_version = be16(0x110B), /* 1.11b, i.e. hacked :-) */
#endif
/* Bitfield enabling general features/codepaths in the firmware or
* selecting support for one of several supported PHYs?
@@ -209,9 +209,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
* 1 X 1 | 0x391C6140 - - -
*/
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- .header.basic_config = be16(0x0404), //original for B50610
+ .header.basic_config = be16(0x0404), /* original for B50610 */
#else
- .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged
+ .header.basic_config = be16(0x0604), /* bit 9 set so not to mess up PHY regs, kept other bits unchanged */
#endif
/* Tag that defines when / on what occasion the commands are interpreted.
@@ -223,7 +223,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
* 68, 20, 70, 80 to be interpreted in this order.
* All tests were performed with .basic_config = 0x0604.
*/
- .init.hunk1_when = 0x10, //only once at RISC CPU reset?
+ .init.hunk1_when = 0x10, /* only once at RISC CPU reset? */
/* Instructions are obviously a specialized bytecode interpreted by the
* main firmware, rather than MIPS machine code. Commands consist of 1-3
* 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable
@@ -245,69 +245,68 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
*/
.init.hunk1_code = {
#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104
- be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel)
- be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105
- be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical)
+ be(0x082B8104), /* CFR-AF: PHY0B: KSZ9021 select PHY104 */
+ be(0x082CF0F0), /* CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) */
+ be(0x082B8105), /* CFR-AF: PHY0B: KSZ9021 select PHY105 */
+ be(0x082C3333), /* CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) */
#endif
- be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch
- be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars
- be(0x06100D38), be(0x00000000), //v1.03 : - |
- be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F|
- }, //-->INIT1_LENGTH!
+ be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), /* v1.05 : 5A0.24,12 = 1: auto-clock-switch */
+ be(0x06100D34), be(0x00000000), /* v1.03 : MemD34: clear config vars */
+ be(0x06100D38), be(0x00000000), /* v1.03 : - | */
+ be(0x06100D3C), be(0x00000000), /* v1.03 : MemD3F| */
+ }, /* -->INIT1_LENGTH! */
- .init.hunk2_when = 0x30, //after global reset, PHY reset
+ .init.hunk2_when = 0x30, /* after global reset, PHY reset */
.init.hunk2_code = {
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08
- be(0x08350001), //v1.06 : PHY15: B50610 slow link fix
- be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08
- be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B
+ be(0x08370F08), /* v1.06 : PHY17: B50610 select reg. 08 */
+ be(0x08350001), /* v1.06 : PHY15: B50610 slow link fix */
+ be(0x08370F00), /* v1.06 : PHY17: B50610 disable reg. 08 */
+ be(0x083C2C00), /* v1.11 : PHY1C: B50610 Shadow 0B */
#endif
- be(0xF7F301E6), //v1.09+: ?: subroutine calls to
- be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ???
- be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?|
- be(0xF7F401E6), //v1.09+: ?|
- }, //-->INIT2_LENGTH!
+ be(0xF7F301E6), /* v1.09+: ?: subroutine calls to */
+ be(0xF7FFF0B6), be(0x0000FFE7), /* v1.09+: ?| restore Port Mode ??? */
+ be(0xF7FFF0F6), be(0x00008000), /* v1.09+: ?| */
+ be(0xF7F401E6), /* v1.09+: ?| */
+ }, /* -->INIT2_LENGTH! */
- .init.hunk3_when = 0xA8, //?, I'd guess quite late
+ .init.hunk3_when = 0xA8, /* ?, I'd guess quite late */
.init.hunk3_code = {
- be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz
- }, //-->INIT3_LENGTH!
+ be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), /* v1.08 : 3604.20-16: 10Mb clock = 12.5MHz */
+ }, /* -->INIT3_LENGTH! */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- .init.hunk4_when = 0xD8, //original for B50610
+ .init.hunk4_when = 0xD8, /* original for B50610 */
#else
- .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up"
+ .init.hunk4_when = 0x80, /* run last, after Linux' "ifconfig up" */
#endif
.init.hunk4_code = {
#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- be(0x083F4300), //CFR-AF: PHY1F: IRQ active high
- be(0x083C0000), //CFR-AF: PHY1C: revert driver writes
- be(0x08380000), //CFR-AF: PHY18|
- be(0x083C0000), //CFR-AF: PHY1C|
+ be(0x083F4300), /* CFR-AF: PHY1F: IRQ active high */
+ be(0x083C0000), /* CFR-AF: PHY1C: revert driver writes */
+ be(0x08380000), /* CFR-AF: PHY18| */
+ be(0x083C0000), /* CFR-AF: PHY1C| */
#endif
- be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes
+ be(0xCB0005A4), be(0xF7F0000C), /* v1.01 : if 5A4.0 == 1 -->skip next 12 bytes */
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode
+ be(0xC61005A4), be(0x3210C500), /* v1.01 : 5A4: PHY LED mode */
#else
- be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode
+ be(0xC61005A4), be(0x331C71CE), /* CFR-AF: 5A4: fake LED mode */
#endif
- be(0xF7F00008), //v1.01 : -->skip next 8 bytes
- be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode
- //be(0xC3200454), //CFR-AF: 454.4: auto link polling
- }, //-->INIT4_LENGTH!
+ be(0xF7F00008), /* v1.01 : -->skip next 8 bytes */
+ be(0xC61005A4), be(0x331C71C1), /* v1.01 : 5A4: inband LED mode */
+ }, /* -->INIT4_LENGTH! */
- .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC
+ .powerdown.hunk1_when = 0x50, /* prior to IDDQ MAC */
.powerdown.hunk1_code = {
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
- be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY
+ be(0x083CB001), /* v1.10 : PHY1C: IDDQ B50610 PHY */
#endif
- be(0xF7F30116), // IDDQ PHY
- be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII
- be(0xC4180400), //v1.09 : 400.3 = 0|
- be(0xC3100400), //v1.09 : 400.2 = 1|
- }, //-->PWRDN_LENGTH!
+ be(0xF7F30116), /* IDDQ PHY */
+ be(0xC40005A0), /* v1.09 : 5A0.0 = 0: Port Mode = MII */
+ be(0xC4180400), /* v1.09 : 400.3 = 0| */
+ be(0xC3100400), /* v1.09 : 400.2 = 1| */
+ }, /* -->PWRDN_LENGTH! */
};
@@ -316,8 +315,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
*/
void broadcom_init(void)
{
- volatile u32 *gec_base; //Gigabit Ethernet Controller base addr
- u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E
+ volatile u32 *gec_base; /* Gigabit Ethernet Controller base addr */
+ u8 *gec_shadow; /* base addr of shadow 'NV'RAM for GbE MAC in A55E */
u8 sum;
int i;
@@ -327,8 +326,8 @@ void broadcom_init(void)
/* Halt RISC CPU before uploading the firmware patch */
for (i = 10000; i > 0; i--) {
- gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state
- gec_base[0x5000/4] |= (1 << 10); //issue RISC halt
+ gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */
+ gec_base[0x5000/4] |= (1 << 10); /* issue RISC halt */
if (gec_base[0x5000/4] | (1 << 10))
break;
udelay(10);
@@ -349,10 +348,10 @@ void broadcom_init(void)
/* Upload firmware patch to shadow 'NV'RAM */
for (i = 0; i < sizeof(selfboot_patch); i++)
- gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise!
+ gec_shadow[i] = ((u8*)&selfboot_patch)[i]; /* access byte-wise! */
/* Restart BCM5785's CPU */
- gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state
- gec_base[0x5000/4] = 0x00000001; //reset RISC processor
- //usually we'd have to wait for the reset bit to clear again ...
+ gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */
+ gec_base[0x5000/4] = 0x00000001; /* reset RISC processor */
+ /* usually we'd have to wait for the reset bit to clear again ... */
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 2deb219..6053ac4 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -86,7 +86,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+ /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index d39a3ab..ea46291 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -161,7 +161,7 @@
* SDIN2 is define at BIT4 & BIT5
* SDIN3 is define at BIT6 & BIT7
*/
-//#define AZALIA_SDIN_PIN 0xAA
+
#define AZALIA_SDIN_PIN 0x2A
/**
More information about the coreboot-gerrit
mailing list