[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/dinar: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 20:53:04 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16968
-gerrit
commit a8e45f59d8ea2b7b78b663489da0210e3fb6fae1
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 20:49:34 2016 +0200
mainboard/amd/dinar: Use C89 comments style & remove commented code
Change-Id: I347810dfe34645bb7c2bf1cfede36ca04e4ef65e
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/dinar/OemCustomize.c | 11 +-
src/mainboard/amd/dinar/OptionsIds.h | 9 -
src/mainboard/amd/dinar/acpi_tables.c | 8 +-
src/mainboard/amd/dinar/buildOpts.c | 107 +++------
src/mainboard/amd/dinar/gpio.c | 427 ++++++++++++++-------------------
src/mainboard/amd/dinar/gpio.h | 418 ++++++++++++++++----------------
src/mainboard/amd/dinar/mainboard.c | 3 -
src/mainboard/amd/dinar/mptable.c | 3 +-
src/mainboard/amd/dinar/platform_cfg.h | 11 +-
src/mainboard/amd/dinar/rd890_cfg.c | 13 +-
src/mainboard/amd/dinar/rd890_cfg.h | 24 +-
src/mainboard/amd/dinar/romstage.c | 4 +-
src/mainboard/amd/dinar/sb700_cfg.c | 34 +--
src/mainboard/amd/dinar/sb700_cfg.h | 3 +-
14 files changed, 480 insertions(+), 595 deletions(-)
diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c
index 84866de..668dd25 100644
--- a/src/mainboard/amd/dinar/OemCustomize.c
+++ b/src/mainboard/amd/dinar/OemCustomize.c
@@ -28,11 +28,12 @@
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- // Dinar has the following routing:
- // CS0 M[B,A]_CLK_H/L[0]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[1]
- // CS3 M[B,A]_CLK_H/L[3]
+ /* Dinar has the following routing:
+ * CS0 M[B,A]_CLK_H/L[0]
+ * CS1 M[B,A]_CLK_H/L[2]
+ * CS2 M[B,A]_CLK_H/L[1]
+ * CS3 M[B,A]_CLK_H/L[3]
+ */
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
PSO_END
diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h
index d1d184d..c9e66d2 100644
--- a/src/mainboard/amd/dinar/OptionsIds.h
+++ b/src/mainboard/amd/dinar/OptionsIds.h
@@ -42,15 +42,6 @@
*
**/
-//#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
-
#endif
diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c
index 1d1717b..425647e 100644
--- a/src/mainboard/amd/dinar/acpi_tables.c
+++ b/src/mainboard/amd/dinar/acpi_tables.c
@@ -72,10 +72,10 @@ unsigned long acpi_fill_madt(unsigned long current)
}
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
- 0, //BUS
- 0, //SOURCE
- 2, //gsirq
- 0 //flags
+ 0, /* BUS */
+ 0, /* SOURCE */
+ 2, /* gsirq */
+ 0 /* flags */
);
/* 0: mean bus 0--->ISA */
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index e237ff0..ee12dfc 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -26,33 +26,32 @@
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
/* AGESA will check the OEM configuration during preprocessing stage,
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
*/
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 /* DDR 400 */
+#define DDR533_FREQUENCY 266 /* DDR 533 */
+#define DDR667_FREQUENCY 333 /* DDR 667 */
+#define DDR800_FREQUENCY 400 /* DDR 800 */
+#define DDR1066_FREQUENCY 533 /* DDR 1066 */
+#define DDR1333_FREQUENCY 667 /* DDR 1333 */
+#define DDR1600_FREQUENCY 800 /* DDR 1600 */
+#define DDR1866_FREQUENCY 933 /* DDR 1866 */
+#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */
/* QUANDRANK_TYPE */
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 /* Use best rate possible */
+#define TIMING_MODE_LIMITED 1 /* Set user top limit */
+#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */
/* Select the CPU family. */
@@ -79,23 +78,9 @@
* Comment out the items wanted to be included in the build.
* Uncomment those items you with to REMOVE from the build.
*/
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
-//#define BLDOPT_REMOVE_SRAT TRUE
-//#define BLDOPT_REMOVE_SLIT TRUE
#define BLDOPT_REMOVE_WHEA TRUE
-//#define BLDOPT_REMOVE_DMI TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
/* Build configuration values here.
*/
#define BLDCFG_VRM_CURRENT_LIMIT 120000
@@ -136,15 +121,11 @@
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000
-//#define BLDCFG_USE_ATM_MODE TRUE
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0
-#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife
-//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000
+#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance /* BatteryLife */
-//#define IDSOPT_IDS_ENABLED TRUE
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
#define BLDCFG_PSTATE_HPC_MODE FALSE
@@ -168,15 +149,17 @@
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
-// This is the delivery package title, "MarG34PI"
-// This string MUST be exactly 8 characters long
+/* This is the delivery package title, "MarG34PI"
+ * This string MUST be exactly 8 characters long
+ */
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
-// This is the release version number of the AGESA component
-// This string MUST be exactly 12 characters long
+/* This is the release version number of the AGESA component
+ * This string MUST be exactly 12 characters long
+ */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '}
-// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
+/* The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. */
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
@@ -195,9 +178,10 @@
#endif
#endif
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
@@ -216,8 +200,8 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
- { //BUID Swap List
- { //BUID Swaps
+ { /* BUID Swap List */
+ { /* BUID Swaps */
/* Each Non-coherent chain may have a list of device swaps,
* Each item specify a device will be swap from its current id to a new one
*/
@@ -233,7 +217,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
},
- { //The ordered final BUIDs
+ { /* The ordered final BUIDs */
/* Specify the final BUID to be zero, All others are non applicable */
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
@@ -251,14 +235,6 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList
-// And another platform specific one ...
-//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] =
-//{
-// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
-// HT_LIST_TERMINAL
-//};
-
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] =
{
{
@@ -282,14 +258,14 @@ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] =
#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList
-// A performance-per-watt optimization.
+/* A performance-per-watt optimization. */
CONST SKIP_REGANG ROMDATA PerfPerWatt[] = {
{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF },
{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF },
{ HT_LIST_TERMINAL }
};
-// uncomment the line below to make Perf-per-watt enabled by default.
+/* uncomment the line below to make Perf-per-watt enabled by default. */
#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt
@@ -313,7 +289,7 @@ CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] =
CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] =
{
- // Source Socket, Link (4-7 are sublink 1), Target Socket
+ /* Source Socket, Link (4-7 are sublink 1), Target Socket */
{0, 0, 1},
{0, 1, 1},
{0, 3, 1},
@@ -329,9 +305,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] =
*/
CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] =
{
- // Socket, Link, SecBus, SubBus
- { 0, 2, 0x00, 0xBF }, // RD890 of Dinar
- { 1, 0, 0xC0, 0xFF }, // HTX
+ /* Socket, Link, SecBus, SubBus */
+ { 0, 2, 0x00, 0xBF }, /* RD890 of Dinar */
+ { 1, 0, 0xC0, 0xFF }, /* HTX */
{ (HT_LIST_TERMINAL) }
};
@@ -346,15 +322,6 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] =
};
#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList
-/*
- CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] =
- {
-// {socketA, linkA, socketB, linkB}
-{0, 0, 1, 1},
-};
-
-#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap
-*/
/*
* Device Capabilities Override for disabling ID Clumping
diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c
index affda6f..56dfb56 100644
--- a/src/mainboard/amd/dinar/gpio.c
+++ b/src/mainboard/amd/dinar/gpio.c
@@ -62,11 +62,11 @@ gpioEarlyInit(
u32 SmiMmioAddr = 0;
u32 andMask32 = 0;
- // Enable HUDSON MMIO Base (AcpiMmioAddr)
+ /* Enable HUDSON MMIO Base (AcpiMmioAddr) */
ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
Data8 |= BIT0;
WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
- // Get HUDSON MMIO Base (AcpiMmioAddr)
+ /* Get HUDSON MMIO Base (AcpiMmioAddr) */
ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
Data16 = Data8 << 8;
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
@@ -77,109 +77,109 @@ gpioEarlyInit(
MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
if ((Data8 & BIT4) == 0) {
- BoardType = 0; // external clock board
+ BoardType = 0; /* external clock board */
}
Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
StripInfo = (Data8 & BIT7) >> 7;
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
StripInfo |= (Data8 & BIT7) >> 6;
- if (StripInfo < boardRevC) { // for old board. Rev B
- Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
- Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
+ if (StripInfo < boardRevC) { /* for old board. Rev B */
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */
}
for (Index = 0; Index < MAX_GPIO_NO; Index++) {
if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
- // Configure multi-function
+ /* Configure multi-function */
Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
}
- // Configure GPIO
+ /* Configure GPIO */
if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
}
if (Index == GPIO_65) {
if ( BoardType == 0 ) {
- Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */
}
}
}
- // Configure GEVENT
+ /* Configure GEVENT */
if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
andMask32 = ~(1 << (Index - GEVENT_00));
- //EventEnable: 0-Disable, 1-Enable
+ /*EventEnable: 0-Disable, 1-Enable */
Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
- //SciTrig: 0-Falling Edge, 1-Rising Edge
+ /*SciTrig: 0-Falling Edge, 1-Rising Edge */
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
- //SciLevl: 0-Edge trigger, 1-Level Trigger
+ /*SciLevl: 0-Edge trigger, 1-Level Trigger */
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
- //SmiSciEn: 0-Not send SMI, 1-Send SMI
+ /*SmiSciEn: 0-Not send SMI, 1-Send SMI */
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
- //SciS0En: 0-Disable, 1-Enable
+ /*SciS0En: 0-Disable, 1-Enable */
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
- //SciMap: 00000b ~ 11111b
+ /*SciMap: 00000b ~ 11111b */
RegIndex8=(u8)((Index - GEVENT_00) >> 2);
Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
- //SmiTrig: 0-Active Low, 1-Active High
+ /*SmiTrig: 0-Active Low, 1-Active High */
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
- //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
+ /*SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */
RegIndex8=(u8)((Index - GEVENT_00) >> 4);
Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
}
}
- //
- // config MXM
- // GPIO9: Input for MXM_PRESENT2#
- // GPIO10: Input for MXM_PRESENT1#
- // GPIO28: Input for MXM_PWRGD
- // GPIO35: Output for MXM Reset
- // GPIO45: Output for MXM Power Enable, active HIGH
- // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
- // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
- //
- // set INTE#/GPIO32 as GPO for PCIE_SW
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO
+ /*
+ * config MXM
+ * GPIO9: Input for MXM_PRESENT2#
+ * GPIO10: Input for MXM_PRESENT1#
+ * GPIO28: Input for MXM_PWRGD
+ * GPIO35: Output for MXM Reset
+ * GPIO45: Output for MXM Power Enable, active HIGH
+ * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
+ * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
+ */
+ /* set INTE#/GPIO32 as GPO for PCIE_SW */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */
RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
- // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
+ /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */
- // set AD9/GPIO9 as GPI for MXM_PRESENT2#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
+ /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */
- // set AD10/GPIO10 as GPI for MXM_PRESENT1#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
+ /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */
- // set GNT1#/GPIO44 as GPO for MXM Reset
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
+ /* set GNT1#/GPIO44 as GPO for MXM Reset */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */
- // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
+ /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */
- // set AD28/GPIO28 as GPI for MXM_PWRGD
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
+ /* set AD28/GPIO28 as GPI for MXM_PWRGD */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */
- // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
+ /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@@ -187,20 +187,13 @@ gpioEarlyInit(
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
- //
- // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
- //
- //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
- //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
+ /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */
- // check if there any GFX card
+ /* check if there any GFX card */
Flags = 0;
- // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
- // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
if (!(Data8 & BIT7))
{
- //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
if (!(Data8 & BIT7))
{
@@ -209,241 +202,187 @@ gpioEarlyInit(
}
if ( Flags )
{
- // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
+ /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
- // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+ /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
- //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
SbStall (10000);
- // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
+ /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
- //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
- // WAIT POWER READY: GPIO28 (MXM_PWRGD)
- //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
+
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
while (!(Data8 & BIT7))
{
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
}
- // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
- // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
}
else
{
- // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
+ /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
- //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
SbStall (10000);
- // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
+ /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
}
- //
- // APU GPP0: On board LAN
- // GPIO25: PCIE_RST#_LAN, LOW active
- // GPIO63: LAN_CLKREQ#
- // GPIO197: LOM_POWER, HIGH Active
- // Clock: GPP_CLK3
- //
- // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
-
- // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3#
- RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
-
- //
- // APU GPP1: WUSB
- // GPIO1: MPCIE_RST2#, LOW active
- // GPIO13: WU_DISABLE#, LOW active
- // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
- //
- // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD01/GPIO01 as GPO for MPCIE_RST2#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
- // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH
- // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- //
- // APU GPP2: WWAN
- // GPIO0: MPCIE_RST1#, LOW active
- // GPIO14: WP_DISABLE#, LOW active
- // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
- //
- // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Set AD00/GPIO00 as GPO for MPCIE_RST1#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
- // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
- // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
-
- //
- // APU GPP3: 1394
- // GPIO59: Power control, HIGH active
- // GPIO27: PCIE_RST#_1394, LOW active
- // GPIO41: CLKREQ#
- // Clock: GPP_CLK8
- //
- // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO
- // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
-
- // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
- // To fix glitch issue
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
- //
- // Enable/Disable OnBoard LAN
- //
+ /*
+ * APU GPP0: On board LAN
+ * GPIO25: PCIE_RST#_LAN, LOW active
+ * GPIO63: LAN_CLKREQ#
+ * GPIO197: LOM_POWER, HIGH Active
+ * Clock: GPP_CLK3
+ *
+ * Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
+ */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+
+ /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */
+
+ /*
+ * APU GPP1: WUSB
+ * GPIO1: MPCIE_RST2#, LOW active
+ * GPIO13: WU_DISABLE#, LOW active
+ * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
+ *
+ * Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
+ */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /*
+ * APU GPP2: WWAN
+ * GPIO0: MPCIE_RST1#, LOW active
+ * GPIO14: WP_DISABLE#, LOW active
+ * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
+ *
+ * Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
+ */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /*
+ * APU GPP3: 1394
+ * GPIO59: Power control, HIGH active
+ * GPIO27: PCIE_RST#_1394, LOW active
+ * GPIO41: CLKREQ#
+ * Clock: GPP_CLK8
+ */
+ /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */
+
+ /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+ /* To fix glitch issue */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */
+
+ /* Enable/Disable OnBoard LAN */
+
if (!CONFIG_ONBOARD_LAN)
- { // 1 - DISABLED
- RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
+ { /* 1 - DISABLED */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
- RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED
- RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3
+ RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */
}
- // else
- // { // 0 - AUTO
- // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
- // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
- // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
- // }
+ /* Enable/Disable 1394 */
- //
- // Enable/Disable 1394
- //
if (!CONFIG_ONBOARD_1394)
- { // 1 - DISABLED
- // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
+ { /* 1 - DISABLED */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
- RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE
- RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8
- // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */
+ RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */
}
- // else
- // { // 0 - AUTO
- // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
- // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
- // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
- //
- // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
- // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
- // }
-
- //
- // external USB 3.0 control:
- // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
- // GPIO26: PCIE_RST#_USB3.0
- // GPIO46: PCIE_USB30_CLKREQ#
- // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
- // Clock: GPP_CLK7
- // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
- // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
- // disable Onboard NEC USB3.0 controller
+
+ /*
+ * external USB 3.0 control:
+ * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
+ * GPIO26: PCIE_RST#_USB3.0
+ * GPIO46: PCIE_USB30_CLKREQ#
+ * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
+ * Clock: GPP_CLK7
+ * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+ */
+
if (!CONFIG_ONBOARD_USB30) {
RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
- RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
- RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7
- RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+ RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */
}
- // }
- //
- // BlueTooth control: BT_ON
- // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
- // GPIO07: BT_ON, 0 - OFF, 1 - ON
- //
+ /* BlueTooth control: BT_ON
+ * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
+ * GPIO07: BT_ON, 0 - OFF, 1 - ON
+ */
if (!CONFIG_ONBOARD_BLUETOOTH) {
- //- if (SystemConfiguration.amdBlueTooth == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
- //- }
}
- //
- // WebCam control:
- // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
- // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
- //
+ /*
+ * WebCam control:
+ * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
+ * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
+ */
if (!CONFIG_ONBOARD_WEBCAM) {
- //- if (SystemConfiguration.amdWebCam == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
- //- }
}
- //
- // Travis enable:
- // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
- // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
- //
+ /*
+ * Travis enable:
+ * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
+ * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
+ */
if (!CONFIG_ONBOARD_TRAVIS) {
- //- if (SystemConfiguration.amdTravisCtrl == 0) {
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
- //- }
}
- //
- // Disable Light Sensor if needed
- //
+ /* Disable Light Sensor if needed */
+
if (CONFIG_ONBOARD_LIGHTSENSOR) {
- //- if (SystemConfiguration.amdLightSensor == 1) {
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
- //- }
}
}
diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h
index 3ac8bfa..d5e96f7 100644
--- a/src/mainboard/amd/dinar/gpio.h
+++ b/src/mainboard/amd/dinar/gpio.h
@@ -83,87 +83,87 @@
#define FUNCTION1 1
#define FUNCTION2 2
#define FUNCTION3 3
-#define NonGpio 0x80 // BIT7
+#define NonGpio 0x80 /* BIT7 */
-// S0-domain General Purpose I/O: GPIO 00~67
-#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED
-#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT
-#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT
-#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED
-#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF
-#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level
-#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED
-#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED
-#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702
-#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711
-#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703
-#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default
-#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted.
-#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
-#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
-#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE
-// 1:BATTERY IS FINE(DEFAULT)
-// 0:BATTERY IS LOW
-#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
-#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default
-#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high
-#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high
-#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high
-#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT
-#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT
-#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0
-#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1
-// 00 - REVA
-// 01 - REVB
-// 10 - REVC
-// 11 - REVD
-#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO
-#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active.
-// 0:USB3.0 I/F in Express CARD
-// 1:PCIE I/F in Express CARD detection
-#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF
-#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH#
-#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC
-#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted.
-#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ#
-#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ#
-#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK
-#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE
-#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
-#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ#
-#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA
-#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ
-#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1
-#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V
-#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1
-#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT
-#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE
-#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE
-#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE)
-// 1:ENABLE; 0:DISABLE
-// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10
-#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN
-#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER
-#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER
-#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE
-#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ#
-#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700
-#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711
-#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ#
-#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703
-#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM
-#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default
-#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT#
+/* S0-domain General Purpose I/O: GPIO 00~67 */
+#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */
+#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */
+#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */
+#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */
+#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */
+#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */
+#define GPIO_06_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */
+#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */
+#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */
+#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */
+#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */
+#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */
+#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */
+#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, /*FUNCTION1, Reset_CEC# Low Active, High default */
+#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */
+#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */
+#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */
+#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */
+/* 1:BATTERY IS FINE(DEFAULT) */
+/* 0:BATTERY IS LOW */
+#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */
+#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */
+#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */
+#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */
+#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */
+#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */
+#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */
+#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */
+#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */
+/* 00 - REVA */
+/* 01 - REVB */
+/* 10 - REVC */
+/* 11 - REVD */
+#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */
+#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */
+/* 0:USB3.0 I/F in Express CARD */
+/* 1:PCIE I/F in Express CARD detection */
+#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */
+#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */
+#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */
+#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */
+#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */
+#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */
+#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */
+#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */
+#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */
+#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */
+#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */
+#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */
+#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */
+#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */
+#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */
+#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */
+#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */
+#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */
+#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */
+/* 1:ENABLE; 0:DISABLE */
+/* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */
+#define GPIO_56_SELECT FUNCTION0+NonGpio /*HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */
+#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */
+#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */
+#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */
+#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */
+#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */
+#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */
+#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */
+#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */
+#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */
+#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */
+#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */
#define GPIO_68_SELECT FUNCTION0+NonGpio
#define GPIO_69_SELECT FUNCTION0+NonGpio
#define GPIO_70_SELECT FUNCTION0+NonGpio
@@ -192,40 +192,40 @@
#define GPIO_93_SELECT FUNCTION0+NonGpio
#define GPIO_94_SELECT FUNCTION0+NonGpio
#define GPIO_95_SELECT FUNCTION0+NonGpio
-// GEVENT 00~23 are mapped to GPIO 96~119
-#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0#
-#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1#
-#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP
-#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI#
-#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT#
-#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active
-#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
-// there is a confliction to IR function when this pin is as a GEVENT.
-#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,
-// special pin difination for SB700 VGA OUTPUT, high active,
-// VGA power for Hudson-M2 will be down when it was asserted.
-#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active
-#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio)
-#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2
-#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0
-#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
-// [option for SPI_TPM_CS# in Hudson-M2 A12)]
-#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
-// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
-#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
-// plus judge GPIO40 and GPIO19 level,low is assert.
-// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default)
-// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option)
-#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active
-#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention,
-// low active, when it's low, BIOS will enbale ODD_PWR
-#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17#
-#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK
-#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST#
-#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT
-#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
-#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED#
-#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI
+/* GEVENT 00~23 are mapped to GPIO 96~119 */
+#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */
+#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */
+#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */
+#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */
+#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */
+#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */
+#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */
+/* there is a confliction to IR function when this pin is as a GEVENT. */
+#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */
+/* special pin difination for SB700 VGA OUTPUT, high active, */
+/* VGA power for Hudson-M2 will be down when it was asserted. */
+#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */
+#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */
+#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */
+#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */
+#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */
+/* [option for SPI_TPM_CS# in Hudson-M2 A12)] */
+#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */
+/* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */
+#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */
+/* plus judge GPIO40 and GPIO19 level,low is assert. */
+/* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */
+/* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */
+#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */
+#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */
+/* low active, when it's low, BIOS will enbale ODD_PWR */
+#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */
+#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */
+#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */
+#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */
+#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */
+#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */
+#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */
#define GPIO_120_SELECT FUNCTION0+NonGpio
#define GPIO_121_SELECT FUNCTION0+NonGpio
#define GPIO_122_SELECT FUNCTION0+NonGpio
@@ -268,78 +268,78 @@
#define GPIO_159_SELECT FUNCTION0+NonGpio
#define GPIO_160_SELECT FUNCTION0+NonGpio
-// S5-domain General Purpose I/O
-#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST#
-#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2
-#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0
-#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1
-#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2
-#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail.
-#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0,
-#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE
-#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3
-#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT#
-#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_178_SELECT FUNCTION2 // MEM_1V5
-#define GPIO_179_SELECT FUNCTION2 // MEM_1V35
-#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO
-#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR
-#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3
-#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0
-#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB#
-#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB
-#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB
-#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE
-#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE
-// option for HDMI CEC signal OW ACTIVE
-#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active
-#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
-#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA
-#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK
-#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK,
-#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA
-#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK,
-#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA
-#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active
-// RESERVED FOR LCD BACKLIGHT PWM
-#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL
-#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM
-#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF
-#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO
-#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO
-#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK,
-#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA
-#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
+/* S5-domain General Purpose I/O */
+#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */
+#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */
+#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */
+#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */
+#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */
+#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */
+#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */
+#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */
+#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */
+#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */
+#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */
+#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */
+#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */
+#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */
+#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */
+#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */
+#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */
+#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */
+#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */
+#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */
+#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */
+#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */
+#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */
+#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */
+/* option for HDMI CEC signal OW ACTIVE */
+#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */
+#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */
+#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */
+#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */
+#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */
+#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */
+#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */
+#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */
+#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */
+/* RESERVED FOR LCD BACKLIGHT PWM */
+#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */
+#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */
+#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */
+#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */
+#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */
+#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */
+#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */
+#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */
#define TYPE_GPI (1 << 5)
#define TYPE_GPO (0 << 5)
@@ -441,7 +441,7 @@
#define GPIO_94_TYPE TYPE_GPO
#define GPIO_95_TYPE TYPE_GPO
-// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119
+/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */
#define GPIO_96_TYPE TYPE_GPI
#define GPIO_97_TYPE TYPE_GPI
#define GPIO_98_TYPE TYPE_GPI
@@ -753,13 +753,13 @@
#define GPO_169_LEVEL GPO_LOW
#define GPO_170_LEVEL GPO_HI
#define GPO_171_LEVEL GPO_LOW
-#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */
#define GPO_173_LEVEL GPO_LOW
#define GPO_174_LEVEL GPO_LOW
#define GPO_175_LEVEL GPO_LOW
#define GPO_176_LEVEL GPO_LOW
#define GPO_177_LEVEL GPO_LOW
-#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU
+#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */
#define GPO_179_LEVEL GPO_HI
#define GPO_180_LEVEL GPO_HI
#define GPO_181_LEVEL GPO_LOW
@@ -1523,28 +1523,28 @@
#define GEVENT_00_EVENTENABLE EVENT_DISABLE
#define GEVENT_01_EVENTENABLE EVENT_DISABLE
-#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP#
-#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI#
-#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT#
-#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN#
+#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */
+#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */
+#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */
+#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */
#define GEVENT_06_EVENTENABLE EVENT_DISABLE
#define GEVENT_07_EVENTENABLE EVENT_DISABLE
#define GEVENT_08_EVENTENABLE EVENT_DISABLE
-#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO
+#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */
#define GEVENT_10_EVENTENABLE EVENT_DISABLE
#define GEVENT_11_EVENTENABLE EVENT_DISABLE
-#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT#
+#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */
#define GEVENT_13_EVENTENABLE EVENT_DISABLE
-#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK#
-#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN#
-#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA
-#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN
+#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */
+#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */
+#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */
+#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */
#define GEVENT_18_EVENTENABLE EVENT_DISABLE
#define GEVENT_19_EVENTENABLE EVENT_DISABLE
#define GEVENT_20_EVENTENABLE EVENT_DISABLE
#define GEVENT_21_EVENTENABLE EVENT_DISABLE
-#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE#
-#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI#
+#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */
+#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */
#define SCITRIG_LOW 0
#define SCITRIG_HI 1
@@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT
typedef struct _GEVENT_SETTINGS
{
- u8 EventEnable; // 0: Disable, 1: Enable
- u8 SciTrig; // 0: Falling Edge, 1: Rising Edge
- u8 SciLevl; // 0: Edge trigger, 1: Level Trigger
- u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI
- u8 SciS0En; // 0: Disable, 1: Enable
- u8 SciMap; // 0000b->1111b
- u8 SmiTrig; // 0: Active Low, 1: Active High
- u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13
+ u8 EventEnable; /* 0: Disable, 1: Enable */
+ u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */
+ u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */
+ u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */
+ u8 SciS0En; /* 0: Disable, 1: Enable */
+ u8 SciMap; /* 0000b->1111b */
+ u8 SmiTrig; /* 0: Active Low, 1: Active High */
+ u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */
} GEVENT_SETTINGS;
GEVENT_SETTINGS gevent_table[] =
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
index 947ec65..ae08ee1 100644
--- a/src/mainboard/amd/dinar/mainboard.c
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -22,8 +22,6 @@
#include <device/pci_def.h>
#include <NbPlatform.h>
-//#define SMBUS_IO_BASE 0x6000
-
void set_pcie_reset(void *nbconfig);
void set_pcie_dereset(void *nbconfig);
@@ -42,7 +40,6 @@ void set_pcie_reset(void *nbconfig)
*/
void set_pcie_dereset(void *nbconfig)
{
- //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
u32 i;
u32 val;
u32 nb_addr;
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index a8b53d0..8780503 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
/* SMBUS */
- //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
/* HD Audio */
PCI_INT(0x0, 0x14, 0x2, 0x10);
@@ -117,7 +116,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
/* SATA */
- PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
+ PCI_INT(0x0, 0x11, 0x0, 0x16); /* 6, INTG */
/* PCI slots */
dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h
index f10e4d7..9afba97 100644
--- a/src/mainboard/amd/dinar/platform_cfg.h
+++ b/src/mainboard/amd/dinar/platform_cfg.h
@@ -21,30 +21,25 @@
/**
* Max number of northbridges in the system
*/
-#define MAX_NB_COUNT 1 //TODO: only 1 NB tested
+#define MAX_NB_COUNT 1 /* TODO: only 1 NB tested */
/**
* Enable check for PCIe endpoint to be ready for PCI enumeration.
*
*/
-//#define EPREADY_WORKAROUND_DISABLED
/**
* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
*
*/
-#define IOMMU_SUPPORT_DISABLE //TODO: enable it
+#define IOMMU_SUPPORT_DISABLE /* TODO: enable it */
/**
* Disable server PCIe hotplug support.
*/
-//#define HOTPLUG_SUPPORT_DISABLED
-
/**
* Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
*/
-//#define DEVICE_REMAP_DISABLE
-
-#endif //_PLATFORM_CFG_H_
+#endif /* _PLATFORM_CFG_H_ */
diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c
index 5459200..733435d 100644
--- a/src/mainboard/amd/dinar/rd890_cfg.c
+++ b/src/mainboard/amd/dinar/rd890_cfg.c
@@ -32,7 +32,6 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
{
u16 i;
PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
- //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
DEFAULT_PLATFORM_CONFIG(platform_config);
@@ -93,7 +92,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
}
}
}
-#endif // __PRE_RAM__
+#endif /* __PRE_RAM__ */
/**
* @brief Entry point of Northbridge CIMx callout/CallBack
@@ -166,9 +165,9 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config)
case CB_AmdSetMidPostConfig:
nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
-#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
+#ifndef IOMMU_SUPPORT_DISABLE /*TODO enable iommu */
/* SBIOS must alloc 16K memory for IOMMU MMIO */
- UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress
+ UINT32 MmcfgBarAddress; /*using default IOmmuBaseAddress */
LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
AccessWidth32,
&MmcfgBarAddress,
@@ -177,7 +176,7 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config)
if (MmcfgBarAddress != 0) {
nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
}
- nbConfigPtr->IommuBaseAddress = 0; //disable iommu
+ nbConfigPtr->IommuBaseAddress = 0; /*disable iommu */
#endif
break;
@@ -235,10 +234,10 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
sbNode = (val >> 8) & 0x07;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
- sbLink = (val >> 8) & 0x07; //assum ganged
+ sbLink = (val >> 8) & 0x07; /*assum ganged */
pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
- //TODO: other NBs
+ /* TODO: other NBs */
#ifndef __PRE_RAM__
/* If temporrary MMIO enable set up CPU MMIO */
diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h
index 8645553..5b5a213 100644
--- a/src/mainboard/amd/dinar/rd890_cfg.h
+++ b/src/mainboard/amd/dinar/rd890_cfg.h
@@ -142,7 +142,6 @@
DEFAULT_GPP2_CONFIG, \
DEFAULT_GPP3A_CONFIG, \
DEFAULT_HT_DEEMPASIES, \
- /*DEFAULT_HT_PATH,*/ \
DEFAULT_APIC_INTERRUPT_BASE, \
}
@@ -150,17 +149,16 @@
* Platform configuration
*/
typedef struct {
- UINT16 PortEnableMap; ///< Bitmap of enabled ports
- UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2
- UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug
- UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors
- UINT32 TemporaryMmio; ///< Temporary MMIO
- UINT32 Gpp1Config; ///< Default PCIe GFX core configuration
- UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration
- UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration
- UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level
- // HT_PATH NbHtPath; ///< HT path to NB
- UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC.
+ UINT16 PortEnableMap; /* Bitmap of enabled ports */
+ UINT16 PortGen1Map; /* Bitmap of ports to disable Gen2 */
+ UINT16 PortHotplugMap; /* Bitmap of ports support hotplug */
+ UINT8 PortHotplugDescriptors[8];/* Ports Hotplug descriptors */
+ UINT32 TemporaryMmio; /* Temporary MMIO */
+ UINT32 Gpp1Config; /* Default PCIe GFX core configuration */
+ UINT32 Gpp2Config; /* Default PCIe GPP2 core configuration */
+ UINT32 Gpp3aConfig; /* Default PCIe GPP3a core configuration */
+ UINT8 NbTransmitterDeemphasis; /* HT transmitter de-emphasis level */
+ UINT8 GlobalApicInterruptBase; /* Global APIC interrupt base that is used in MADT table for IO APIC. */
} NB_PLATFORM_CONFIG;
/**
@@ -168,4 +166,4 @@ typedef struct {
*/
void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
-#endif //_RD890_CFG_H_
+#endif /* _RD890_CFG_H_ */
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index bc5d312..a1b1e3b 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -64,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x33);
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
@@ -101,5 +101,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x44);
copy_and_run();
- post_code(0x45); // Should never see this post code.
+ post_code(0x45); /* Should never see this post code. */
}
diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c
index 797bed8..2a5eae3 100644
--- a/src/mainboard/amd/dinar/sb700_cfg.c
+++ b/src/mainboard/amd/dinar/sb700_cfg.c
@@ -83,8 +83,8 @@ void sb700_cimx_config(AMDSBCFG *sb_config)
sb_config->SpreadSpectrum = 0;
sb_config->PciClk5 = 0;
sb_config->PciClks = 0x1F;
- sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
- sb_config->TimerClockSource = 2; // Auto
+ sb_config->ResetCpuOnSyncFlood = 1; /* Do not reset CPU on sync flood */
+ sb_config->TimerClockSource = 2; /* Auto */
sb_config->S3Resume = 0;
sb_config->RebootRequired = 0;
@@ -92,28 +92,28 @@ void sb700_cimx_config(AMDSBCFG *sb_config)
sb_config->HpetTimer = HPET_TIMER;
/* USB */
- sb_config->UsbIntClock = 0; // Use external clock
- sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0
- sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1
- sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2
- sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0
- sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1
- sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2
- sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5
- sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable
+ sb_config->UsbIntClock = 0; /* Use external clock */
+ sb_config->Usb1Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func0 */
+ sb_config->Usb1Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func1 */
+ sb_config->Usb1Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func2 */
+ sb_config->Usb2Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func0 */
+ sb_config->Usb2Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func1 */
+ sb_config->Usb2Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func2 */
+ sb_config->Usb3Ohci = 1; /* 0:disable 1:enable Bus 0 Dev 20 Func5 */
+ sb_config->UsbOhciLegacyEmulation = 1; /* 0:Enable 1:Disable */
sb_config->AcpiS1Supported = 1;
/* SATA */
sb_config->SataController = 1;
- sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
+ sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; /* 0 native, 1 raid, 2 ahci */
sb_config->SataSmbus = 0;
sb_config->SataAggrLinkPmCap = 1;
sb_config->SataPortMultCap = 1;
sb_config->SataClkAutoOff = 1;
- sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
- //TODO: set to secondary not take effect.
- sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
+ sb_config->SataIdeCombMdPriSecOpt = 0; /* 0 -IDE as primary, 1 -IDE as secondary. */
+ /* TODO: set to secondary not take effect. */
+ sb_config->SataIdeCombinedMode = 0; /* 1 IDE controlor exposed and combined mode enabled, 0 disabled */
sb_config->SataEspPort = 0;
sb_config->SataClkAutoOffAhciMode = 1;
sb_config->SataHpcpButNonESP = 0;
@@ -134,7 +134,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config)
sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry;
}
- //sb_config->
-#endif //!__PRE_RAM__
+ /* sb_config-> */
+#endif /* !__PRE_RAM__ */
printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__);
}
diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h
index 02c3934..65327bf 100644
--- a/src/mainboard/amd/dinar/sb700_cfg.h
+++ b/src/mainboard/amd/dinar/sb700_cfg.h
@@ -187,7 +187,6 @@
* SDIN3 is define at BIT6 & BIT7
*/
#ifndef AZALIA_SDIN_PIN
-//#define AZALIA_SDIN_PIN 0xAA
#define AZALIA_SDIN_PIN
#define AZALIA_SDIN_PIN_0 0x2
#define AZALIA_SDIN_PIN_1 0x2
@@ -234,4 +233,4 @@ void sb700_cimx_config(AMDSBCFG *sb_cfg);
*/
u32 sb700_callout_entry(u32 func, u32 data, void* config);
-#endif //_SB700_CFG_H_
+#endif /* _SB700_CFG_H_ */
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