[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/parmer: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 21:20:46 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16973
-gerrit
commit 8d7438d4c8b6108dc3b61d2e77dfcd54b123a3c7
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 21:16:08 2016 +0200
mainboard/amd/parmer: Use C89 comments style & remove commented code
Change-Id: Ia01281bc18a0021792a25bab5334ab676f8a233c
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/parmer/BiosCallOuts.c | 26 +++---
src/mainboard/amd/parmer/OptionsIds.h | 10 ---
src/mainboard/amd/parmer/buildOpts.c | 140 ++++++++++----------------------
src/mainboard/amd/parmer/mptable.c | 1 -
4 files changed, 54 insertions(+), 123 deletions(-)
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c
index c83e318..e4862f3 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.c
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* Thermal Zone Parameter */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
@@ -138,15 +138,15 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* IMC Fan Policy temperature thresholds */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /* AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /* AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /* AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /* AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /* AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /* AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /* AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /* critical threshold* in Celsius, 0xFF is not define */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
/* IMC Fan Policy PWM Settings */
@@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
- FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
@@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE;
diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h
index eaf2442..bf623f7 100644
--- a/src/mainboard/amd/parmer/OptionsIds.h
+++ b/src/mainboard/amd/parmer/OptionsIds.h
@@ -43,17 +43,7 @@
**/
#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
-//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
#endif
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 8ba3c53..acf86b6 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -50,35 +50,22 @@
#define INSTALL_FM2_SOCKET_SUPPORT FALSE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
-#define BLDOPT_REMOVE_SRAT FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_DMI TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+/* This element selects whether P-States should be forced to be independent,
+ * as reported by the ACPI _PSD object. For single-link processors,
+ * setting TRUE for OS to support this feature.
+ */
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -126,7 +113,7 @@
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
#define BLDOPT_REMOVE_ALIB FALSE
@@ -138,16 +125,10 @@
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
#define BLDCFG_CFG_ABM_SUPPORT 0
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+/* Specify the default values for the VRM controlling the VDDNB plane.
+ * If not specified, the values used for the core VRM will be applied
+ */
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
@@ -157,17 +138,14 @@
#if CONFIG_GFXUMA
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* 512M */
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT FALSE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
@@ -175,43 +153,7 @@
/*
* Customized OEM build configurations for FCH component
*/
-// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
-// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
-// #define BLDCFG_AZALIA_SSID 0x780D1022
-// #define BLDCFG_SMBUS_SSID 0x780B1022
-// #define BLDCFG_IDE_SSID 0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID 0x78011022
-// #define BLDCFG_SATA_IDE_SSID 0x78001022
-// #define BLDCFG_SATA_RAID5_SSID 0x78031022
-// #define BLDCFG_SATA_RAID_SSID 0x78021022
-// #define BLDCFG_EHCI_SSID 0x78081022
-// #define BLDCFG_OHCI_SSID 0x78071022
-// #define BLDCFG_LPC_SSID 0x780E1022
-// #define BLDCFG_SD_SSID 0x78061022
-// #define BLDCFG_XHCI_SSID 0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
@@ -245,40 +187,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#include "cpuLateInit.h"
#include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 /* DDR 400 */
+#define DDR533_FREQUENCY 266 /* DDR 533 */
+#define DDR667_FREQUENCY 333 /* DDR 667 */
+#define DDR800_FREQUENCY 400 /* DDR 800 */
+#define DDR1066_FREQUENCY 533 /* DDR 1066 */
+#define DDR1333_FREQUENCY 667 /* DDR 1333 */
+#define DDR1600_FREQUENCY 800 /* DDR 1600 */
+#define DDR1866_FREQUENCY 933 /* DDR 1866 */
+#define DDR2100_FREQUENCY 1050 /* DDR 2100 */
+#define DDR2133_FREQUENCY 1066 /* DDR 2133 */
+#define DDR2400_FREQUENCY 1200 /* DDR 2400 */
+#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 /* Use best rate possible */
+#define TIMING_MODE_LIMITED 1 /* Set user top limit */
+#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */
/*
* Agesa optional capabilities selection.
@@ -323,7 +265,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL parmer_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},
@@ -331,9 +272,10 @@ GPIO_CONTROL parmer_gpio[] = {
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index e10fc89..b630b71 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
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