[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/olivehill: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 21:14:11 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16972
-gerrit
commit c9e2f08d0d06bd638d4a10d4f96d154df3fe7186
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 21:08:15 2016 +0200
mainboard/amd/olivehill: Use C89 comments style & remove commented code
Change-Id: Idfe6a0dcc8bed160755c9386a2131f1caf1d9b4d
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/olivehill/BiosCallOuts.c | 54 ++++++------
src/mainboard/amd/olivehill/OptionsIds.h | 10 ---
src/mainboard/amd/olivehill/buildOpts.c | 129 ++++++-----------------------
src/mainboard/amd/olivehill/mptable.c | 39 ---------
4 files changed, 54 insertions(+), 178 deletions(-)
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
index 2361c03..5774d70 100644
--- a/src/mainboard/amd/olivehill/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -45,20 +45,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
* AMD Olivehill Platform ALC272 Verb Table
*/
static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
- {0x11, 0x411111F0}, // - SPDIF_OUT2
- {0x12, 0x411111F0}, // - DMIC_1/2
- {0x13, 0x411111F0}, // - DMIC_3/4
- {0x14, 0x411111F0}, // Port D - LOUT1
- {0x15, 0x411111F0}, // Port A - LOUT2
- {0x16, 0x411111F0}, //
- {0x17, 0x411111F0}, // Port H - MONO
- {0x18, 0x01a19840}, // Port B - MIC1
- {0x19, 0x411111F0}, // Port F - MIC2
- {0x1a, 0x01813030}, // Port C - LINE1
- {0x1b, 0x411111F0}, // Port E - LINE2
- {0x1d, 0x40130605}, // - PCBEEP
- {0x1e, 0x01441120}, // - SPDIF_OUT1
- {0x21, 0x01214010}, // Port I - HPOUT
+ {0x11, 0x411111F0}, /* - SPDIF_OUT2 */
+ {0x12, 0x411111F0}, /* - DMIC_1/2 */
+ {0x13, 0x411111F0}, /* - DMIC_3/4 */
+ {0x14, 0x411111F0}, /* Port D - LOUT1 */
+ {0x15, 0x411111F0}, /* Port A - LOUT2 */
+ {0x16, 0x411111F0},
+ {0x17, 0x411111F0}, /* Port H - MONO */
+ {0x18, 0x01a19840}, /* Port B - MIC1 */
+ {0x19, 0x411111F0}, /* Port F - MIC2 */
+ {0x1a, 0x01813030}, /* Port C - LINE1 */
+ {0x1b, 0x411111F0}, /* Port E - LINE2 */
+ {0x1d, 0x40130605}, /* - PCBEEP */
+ {0x1e, 0x01441120}, /* - SPDIF_OUT1 */
+ {0x21, 0x01214010}, /* Port I - HPOUT */
{0xff, 0xffffffff}
};
@@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* Thermal Zone Parameter */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3 */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
@@ -138,15 +138,15 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* IMC Fan Policy temperature thresholds */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /* AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /* AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /* AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /* AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /* AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /* AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /* AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /* critical threshold* in Celsius, 0xFF is not define */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
/* IMC Fan Policy PWM Settings */
@@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
- FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
@@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ /* logical devicd 3 */
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h
index eaf2442..bf623f7 100644
--- a/src/mainboard/amd/olivehill/OptionsIds.h
+++ b/src/mainboard/amd/olivehill/OptionsIds.h
@@ -43,17 +43,7 @@
**/
#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
-//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
#endif
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 1d3fe77..60ef481 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -53,36 +53,22 @@
#endif
#endif
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
-#define BLDOPT_REMOVE_SRAT FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_CDIT TRUE
#define BLDOPT_REMOVE_DMI TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+/*This element selects whether P-States should be forced to be independent,
+ * as reported by the ACPI _PSD object. For single-link processors,
+ * setting TRUE for OS to support this feature.
+ */
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -104,11 +90,12 @@
#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
- // core for C-state entry requests. A value
- // of 0 in this field specifies that the core
- // does not trap any IO addresses for C-state entry.
- // Values greater than 0xFFF8 results in undefined behavior.
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the
+ * core for C-state entry requests. A value
+ * of 0 in this field specifies that the core
+ * does not trap any IO addresses for C-state entry.
+ * Values greater than 0xFFF8 results in undefined behavior.
+ */
#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
@@ -149,15 +136,10 @@
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
#define BLDCFG_IOMMU_SUPPORT FALSE
#define OPTION_GFX_INIT_SVIEW FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
#define BLDCFG_CFG_ABM_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
#ifdef PCIEX_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
@@ -174,43 +156,6 @@
/*
* Customized OEM build configurations for FCH component
*/
-// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
-// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
-// #define BLDCFG_AZALIA_SSID 0x780D1022
-// #define BLDCFG_SMBUS_SSID 0x780B1022
-// #define BLDCFG_IDE_SSID 0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID 0x78011022
-// #define BLDCFG_SATA_IDE_SSID 0x78001022
-// #define BLDCFG_SATA_RAID5_SSID 0x78031022
-// #define BLDCFG_SATA_RAID_SSID 0x78021022
-// #define BLDCFG_EHCI_SSID 0x78081022
-// #define BLDCFG_OHCI_SSID 0x78071022
-// #define BLDCFG_LPC_SSID 0x780E1022
-// #define BLDCFG_SD_SSID 0x78061022
-// #define BLDCFG_XHCI_SSID 0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
{
@@ -244,40 +189,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "cpuLateInit.h"
#include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-//#define DDR400_FREQUENCY 200 ///< DDR 400
-//#define DDR533_FREQUENCY 266 ///< DDR 533
-//#define DDR667_FREQUENCY 333 ///< DDR 667
-//#define DDR800_FREQUENCY 400 ///< DDR 800
-//#define DDR1066_FREQUENCY 533 ///< DDR 1066
-//#define DDR1333_FREQUENCY 667 ///< DDR 1333
-//#define DDR1600_FREQUENCY 800 ///< DDR 1600
-//#define DDR1866_FREQUENCY 933 ///< DDR 1866
-//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
-//
-///* QUANDRANK_TYPE*/
-//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
-//
-///* USER_MEMORY_TIMING_MODE */
-//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
-//
-///* POWER_DOWN_MODE */
-//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/* QUANDRANK_TYPE*/
+
+/* USER_MEMORY_TIMING_MODE */
+
+/* POWER_DOWN_MODE */
/*
* Agesa optional capabilities selection.
@@ -322,17 +248,16 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL olivehill_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},
{-1}
};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 9ae75ae..a540d0d 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
@@ -102,45 +101,7 @@ static void *smp_write_config_table(void *v)
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
-#if 0
- outb(0x0B, 0xCD6);
- outb(0x02, 0xCD7);
- outb(0x50, 0xCD6);
- outb(0x1F, 0xCD7);
-
- outb(0x48, 0xCD6);
- outb(0xF2, 0xCD7);
-
- //outb(0xBE, 0xCD6);
- //outb(0x52, 0xCD7);
-
- outb(0xED, 0xCD6);
- outb(0x17, 0xCD7);
-
- *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
- *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
- *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
- *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
- *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
-
- *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
-#endif
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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