[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/torpedo: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 21:44:46 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16979
-gerrit
commit 4e7846bcf5920b9e78da37d89232b6ecd21c1768
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 21:42:37 2016 +0200
mainboard/amd/torpedo: Use C89 comments style & remove commented code
Change-Id: I5e74dfd0672ba5702da0b8b67622331bd756b6ba
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/torpedo/BiosCallOuts.c | 36 +-
src/mainboard/amd/torpedo/Oem.h | 23 +-
src/mainboard/amd/torpedo/OemCustomize.c | 30 +-
src/mainboard/amd/torpedo/OptionsIds.h | 9 -
src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 72 ++--
src/mainboard/amd/torpedo/buildOpts.c | 41 +-
src/mainboard/amd/torpedo/fadt.c | 1 -
src/mainboard/amd/torpedo/gpio.c | 437 +++++++++------------
src/mainboard/amd/torpedo/gpio.h | 418 ++++++++++----------
src/mainboard/amd/torpedo/mainboard.c | 1 -
src/mainboard/amd/torpedo/mptable.c | 3 -
src/mainboard/amd/torpedo/platform_cfg.h | 47 +--
src/mainboard/amd/torpedo/romstage.c | 4 +-
13 files changed, 499 insertions(+), 623 deletions(-)
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index 0035a27..13c22eb 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -105,7 +105,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
- // Get SB MMIO Base (AcpiMmioAddr)
+ /* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
@@ -117,15 +117,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
if (ResetInfo->ResetControl == DeassertSlotReset) {
- if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
- // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { /* de-assert */
+ /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
if (Data8 & BIT7) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
while (!(Data8 & BIT7)) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
}
- // GPIO44: PE_GPIO0 MXM Reset
+ /* GPIO44: PE_GPIO0 MXM Reset */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
@@ -134,53 +134,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
} else {
Status = AGESA_UNSUPPORTED;
}
- // Travis
+ /* Travis */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
- //DE-Assert ALL PCIE RESET
- // APU GPP0 (Dev 4)
+ /* DE-Assert ALL PCIE RESET */
+ /* APU GPP0 (Dev 4) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
- // APU GPP1 (Dev 5)
+ /* APU GPP1 (Dev 5) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
- // APU GPP2 (Dev 6)
+ /* APU GPP2 (Dev 6) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
- // APU GPP3 (Dev 7)
+ /* APU GPP3 (Dev 7) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
} else {
- if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
- // GPIO44: PE_GPIO0 MXM Reset
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { /* Pcie Slot Reset is supported */
+ /* GPIO44: PE_GPIO0 MXM Reset */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
Status = AGESA_SUCCESS;
}
- // Travis
+ /* Travis */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
- //Assert ALL PCIE RESET
- // APU GPP0 (Dev 4)
+ /* Assert ALL PCIE RESET */
+ /* APU GPP0 (Dev 4) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
- // APU GPP1 (Dev 5)
+ /* APU GPP1 (Dev 5) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
- // APU GPP2 (Dev 6)
+ /* APU GPP2 (Dev 6) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
- // APU GPP3 (Dev 7)
+ /* APU GPP3 (Dev 7) */
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
index 0910ddc..86ececc 100644
--- a/src/mainboard/amd/torpedo/Oem.h
+++ b/src/mainboard/amd/torpedo/Oem.h
@@ -13,16 +13,13 @@
* GNU General Public License for more details.
*/
#ifndef BIOS_SIZE
- #define BIOS_SIZE 0x04 //04 - 1MB
+ #define BIOS_SIZE 0x04 /* 04 - 1MB */
#endif
#define LEGACY_FREE 0x00
#if !CONFIG_ONBOARD_USB30
#define XHCI_SUPPORT 0x01
#endif
-//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot.
-//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
-
/**
* Module Specific Defines for platform BIOS
*
@@ -74,7 +71,7 @@
*
*/
#ifndef WATCHDOG_TIMER_BASE_ADDRESS
- #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
+ #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 /* Watchdog Timer Base Address */
#endif
/**
@@ -82,7 +79,7 @@
*
*/
#ifndef HPET_BASE_ADDRESS
- #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
+ #define HPET_BASE_ADDRESS 0xFED00000 /* HPET Base address */
#endif
/**
@@ -107,43 +104,43 @@
* PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
*
*/
-#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
+#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET /* AcpiPm1EvtBlkAddr */
/**
* PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
*
*/
-#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
+#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET /* AcpiPm1CntBlkAddr */
/**
* PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
*
*/
-#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
+#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET /* AcpiPmTmrBlkAddr */
/**
* CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
*
*/
-#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
+#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET /* CpuControlBlkAddr */
/**
* GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
*
*/
-#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
+#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET /* AcpiGpe0BlkAddr */
/**
* SMI_CMD_PORT - ACPI SMI Command block base address
*
*/
-#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
+#define SMI_CMD_PORT 0xB0 /* SmiCmdPortAddr */
/**
* ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
*
*/
-#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
+#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 /* AcpiPmaCntBlkAddr */
/**
* SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 3c20047..cba36bb 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -23,58 +23,53 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
- // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
},
- // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
},
- // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
- // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
- // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
- // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}
- // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-// {
-// DESCRIPTOR_TERMINATE_LIST,
-// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8),
-// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
-// }
+ /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */
};
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
- // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
+ /* Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
},
- // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
+ /* Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
@@ -114,11 +109,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams;
- // GNB PCIe topology Porting
+ /* GNB PCIe topology Porting */
+
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
- //
- // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
- //
AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h
index 45abcab..77e1e90 100644
--- a/src/mainboard/amd/torpedo/OptionsIds.h
+++ b/src/mainboard/amd/torpedo/OptionsIds.h
@@ -42,15 +42,6 @@
*
**/
-//#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
-
#endif
diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
index 001ed16..0e0255e 100644
--- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
@@ -20,45 +20,45 @@
#include "AGESA.h"
#include "amdlib.h"
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port4 */
+#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port5 */
+#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port6 */
+#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port7 */
+#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port8 */
+#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
+#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 656102d..24213cf 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -79,7 +79,7 @@
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
-//For revision C single-link processors
+/* For revision C single-link processors */
#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE
@@ -96,12 +96,12 @@
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
- // This is the delivery package title, "LlanoPI "
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "LlanoPI " */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
/* The following definitions specify the default values for various parameters
@@ -119,8 +119,8 @@
/* Build configuration values here.
*/
-#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0
+#define BLDCFG_VRM_CURRENT_LIMIT 65000 /* 240000 */ /*120000 */
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 /* 0 */
#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
#define BLDCFG_PLAT_NUM_IO_APICS 3
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
@@ -128,7 +128,7 @@
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY /* DDR1066_FREQUENCY */
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
@@ -161,23 +161,14 @@
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
-//enable HW C1E
-#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware
-//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415
-#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
+/* enable HW C1E */
+#define BLDCFG_PLATFORM_C1E_MODE 0 /* C1eModeHardware */
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 /* 0 */
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 /* Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 */
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero.
-//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero.
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 /* Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. */
#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE
#define BLDCFG_STEREO_3D_PINOUT TRUE
@@ -202,12 +193,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
-//#define OPTION_NB_LCLK_DPM_INIT FALSE
-//#define OPTION_POWER_GATE FALSE
-//#define OPTION_PCIE_POWER_GATE FALSE
-//#define OPTION_ALIB FALSE
-//#define OPTION_PCIe_MID_INIT FALSE
-//#define OPTION_NB_MID_INIT FALSE
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index 56a90a6..5b34b9d 100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
*/
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 03ab409..d3e905c 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -56,11 +56,11 @@ void gpioEarlyInit(void) {
u32 SmiMmioAddr = 0;
u32 andMask32 = 0;
- // Enable HUDSON MMIO Base (AcpiMmioAddr)
+ /* Enable HUDSON MMIO Base (AcpiMmioAddr) */
ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
Data8 |= BIT0;
WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
- // Get HUDSON MMIO Base (AcpiMmioAddr)
+ /* Get HUDSON MMIO Base (AcpiMmioAddr) */
ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
Data16 = Data8 << 8;
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
@@ -71,109 +71,109 @@ void gpioEarlyInit(void) {
MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
if ((Data8 & BIT4) == 0) {
- BoardType = 0; // external clock board
+ BoardType = 0; /* external clock board */
}
Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
StripInfo = (Data8 & BIT7) >> 7;
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
StripInfo |= (Data8 & BIT7) >> 6;
- if (StripInfo < boardRevC) { // for old board. Rev B
- Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
- Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
+ if (StripInfo < boardRevC) { /* for old board. Rev B */
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */
}
for (Index = 0; Index < MAX_GPIO_NO; Index++) {
if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
- // Configure multi-function
+ /* Configure multi-function */
Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
}
- // Configure GPIO
+ /* Configure GPIO */
if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
}
if (Index == GPIO_65) {
if ( BoardType == 0 ) {
- Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
+ Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */
}
}
}
- // Configure GEVENT
+ /* Configure GEVENT */
if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
andMask32 = ~(1 << (Index - GEVENT_00));
- //EventEnable: 0-Disable, 1-Enable
+ /* EventEnable: 0-Disable, 1-Enable */
Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
- //SciTrig: 0-Falling Edge, 1-Rising Edge
+ /* SciTrig: 0-Falling Edge, 1-Rising Edge */
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
- //SciLevl: 0-Edge trigger, 1-Level Trigger
+ /* SciLevl: 0-Edge trigger, 1-Level Trigger */
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
- //SmiSciEn: 0-Not send SMI, 1-Send SMI
+ /* SmiSciEn: 0-Not send SMI, 1-Send SMI */
Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
- //SciS0En: 0-Disable, 1-Enable
+ /* SciS0En: 0-Disable, 1-Enable */
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
- //SciMap: 00000b ~ 11111b
+ /* SciMap: 00000b ~ 11111b */
RegIndex8 = (u8)((Index - GEVENT_00) >> 2);
Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8);
Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
- //SmiTrig: 0-Active Low, 1-Active High
+ /* SmiTrig: 0-Active Low, 1-Active High */
Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
- //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
+ /* SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */
RegIndex8 = (u8)((Index - GEVENT_00) >> 4);
Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2);
Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
}
}
- //
- // config MXM
- // GPIO9: Input for MXM_PRESENT2#
- // GPIO10: Input for MXM_PRESENT1#
- // GPIO28: Input for MXM_PWRGD
- // GPIO35: Output for MXM Reset
- // GPIO45: Output for MXM Power Enable, active HIGH
- // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
- // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
- //
- // set INTE#/GPIO32 as GPO for PCIE_SW
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO
+ /*
+ * config MXM
+ * GPIO9: Input for MXM_PRESENT2#
+ * GPIO10: Input for MXM_PRESENT1#
+ * GPIO28: Input for MXM_PWRGD
+ * GPIO35: Output for MXM Reset
+ * GPIO45: Output for MXM Power Enable, active HIGH
+ * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
+ * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
+ */
+ /* set INTE#/GPIO32 as GPO for PCIE_SW */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */
RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
- // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
+ /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */
- // set AD9/GPIO9 as GPI for MXM_PRESENT2#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
+ /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */
- // set AD10/GPIO10 as GPI for MXM_PRESENT1#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
+ /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */
- // set GNT1#/GPIO44 as GPO for MXM Reset
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
+ /* set GNT1#/GPIO44 as GPO for MXM Reset */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */
- // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
+ /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */
- // set AD28/GPIO28 as GPI for MXM_PWRGD
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
+ /* set AD28/GPIO28 as GPI for MXM_PWRGD */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */
- // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
+ /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@@ -181,20 +181,13 @@ void gpioEarlyInit(void) {
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
- //
- // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
- //
- //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
- //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
+ /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */
- // check if there any GFX card
+ /* check if there any GFX card */
Flags = 0;
- // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
- // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
if (!(Data8 & BIT7))
{
- //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
if (!(Data8 & BIT7))
{
@@ -203,241 +196,193 @@ void gpioEarlyInit(void) {
}
if (Flags)
{
- // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
+ /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
- // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+ /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
- //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+ /*PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) */
SbStall (10000);
- // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
+ /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
- //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
- // WAIT POWER READY: GPIO28 (MXM_PWRGD)
- //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
+ /* WAIT POWER READY: GPIO28 (MXM_PWRGD) */
+
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
while (!(Data8 & BIT7))
{
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
}
- // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
- //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
+ /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset */
+ /* RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); */
}
else
{
- // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
+ /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
- //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
SbStall (10000);
- // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
+ /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
}
- //
- // APU GPP0: On board LAN
- // GPIO25: PCIE_RST#_LAN, LOW active
- // GPIO63: LAN_CLKREQ#
- // GPIO197: LOM_POWER, HIGH Active
- // Clock: GPP_CLK3
- //
- // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
-
- // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3#
- RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
-
- //
- // APU GPP1: WUSB
- // GPIO1: MPCIE_RST2#, LOW active
- // GPIO13: WU_DISABLE#, LOW active
- // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
- //
- // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD01/GPIO01 as GPO for MPCIE_RST2#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
-// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH
-// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- //
- // APU GPP2: WWAN
- // GPIO0: MPCIE_RST1#, LOW active
- // GPIO14: WP_DISABLE#, LOW active
- // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
- //
- // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Set AD00/GPIO00 as GPO for MPCIE_RST1#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
-// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
-// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
-
- //
- // APU GPP3: 1394
- // GPIO59: Power control, HIGH active
- // GPIO27: PCIE_RST#_1394, LOW active
- // GPIO41: CLKREQ#
- // Clock: GPP_CLK8
- //
- // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO
-// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
-
- // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
-
- // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
- RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
- // To fix glitch issue
- RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
- //
- // Enable/Disable OnBoard LAN
- //
+ /*
+ * APU GPP0: On board LAN
+ * GPIO25: PCIE_RST#_LAN, LOW active
+ * GPIO63: LAN_CLKREQ#
+ * GPIO197: LOM_POWER, HIGH Active
+ * Clock: GPP_CLK3
+ */
+ /* Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+
+ /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */
+
+ /*
+ * APU GPP1: WUSB
+ * GPIO1: MPCIE_RST2#, LOW active
+ * GPIO13: WU_DISABLE#, LOW active
+ * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
+ */
+ /* Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB */
+
+
+ /*
+ * APU GPP2: WWAN
+ * GPIO0: MPCIE_RST1#, LOW active
+ * GPIO14: WP_DISABLE#, LOW active
+ * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
+ */
+ /* Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN */
+
+ /*
+ * APU GPP3: 1394
+ * GPIO59: Power control, HIGH active
+ * GPIO27: PCIE_RST#_1394, LOW active
+ * GPIO41: CLKREQ#
+ * Clock: GPP_CLK8
+ */
+ /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+
+ /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */
+
+ /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */
+ RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */
+ /* To fix glitch issue */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */
+
+ /* Enable/Disable OnBoard LAN */
+
if (!CONFIG_ONBOARD_LAN)
- { // 1 - DISABLED
- RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
+ { /* 1 - DISABLED */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
- RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED
- RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3
+ RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */
}
-// else
-// { // 0 - AUTO
-// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
-// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
-// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
-// }
+ /* Enable/Disable 1394 */
- //
- // Enable/Disable 1394
- //
if (!CONFIG_ONBOARD_1394)
- { // 1 - DISABLED
-// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
- RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
+ { /* 1 - DISABLED */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
- RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE
- RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8
-// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH
+ RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */
+ RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */
}
-// else
-// { // 0 - AUTO
-// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
-// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
-// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
-//
-// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
-// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
-// }
-
-//
-// external USB 3.0 control:
-// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
-// GPIO26: PCIE_RST#_USB3.0
-// GPIO46: PCIE_USB30_CLKREQ#
-// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
-// Clock: GPP_CLK7
-// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
-// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
-// disable Onboard NEC USB3.0 controller
+
+/*
+ * external USB 3.0 control:
+ * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
+ * GPIO26: PCIE_RST#_USB3.0
+ * GPIO46: PCIE_USB30_CLKREQ#
+ * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
+ * Clock: GPP_CLK7
+ * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+ */
+/* disable Onboard NEC USB3.0 controller */
if (!CONFIG_ONBOARD_USB30) {
RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
- RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
- RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7
- RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+ RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */
+ RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */
+ RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */
}
-// }
-
-//
-// BlueTooth control: BT_ON
-// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
-// GPIO07: BT_ON, 0 - OFF, 1 - ON
-//
+/*
+ * BlueTooth control: BT_ON
+ * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
+ * GPIO07: BT_ON, 0 - OFF, 1 - ON
+ */
if (!CONFIG_ONBOARD_BLUETOOTH) {
- //- if (SystemConfiguration.amdBlueTooth == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
- //- }
}
-//
-// WebCam control:
-// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
-// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
-//
+/*
+ * WebCam control:
+ * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
+ * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
+ */
if (!CONFIG_ONBOARD_WEBCAM) {
- //- if (SystemConfiguration.amdWebCam == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
- //- }
}
-//
-// Travis enable:
-// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
-// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
-//
+/*
+ * Travis enable:
+ * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
+ * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
+ */
if (!CONFIG_ONBOARD_TRAVIS) {
- //- if (SystemConfiguration.amdTravisCtrl == 0) {
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
- //- }
}
-//
-// Disable Light Sensor if needed
-//
+
+/* Disable Light Sensor if needed */
+
if (CONFIG_ONBOARD_LIGHTSENSOR) {
- //- if (SystemConfiguration.amdLightSensor == 1) {
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
- //- }
}
-
}
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
index 0df5d50..e3d0c03 100644
--- a/src/mainboard/amd/torpedo/gpio.h
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -83,87 +83,87 @@
#define FUNCTION1 1
#define FUNCTION2 2
#define FUNCTION3 3
-#define NonGpio 0x80 // BIT7
+#define NonGpio 0x80 /* BIT7 */
-// S0-domain General Purpose I/O: GPIO 00~67
-#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED
-#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT
-#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT
-#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED
-#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF
-#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level
-#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED
-#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED
-#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702
-#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711
-#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703
-#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default
-#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted.
-#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
-#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
-#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE
- // 1:BATTERY IS FINE(DEFAULT)
- // 0:BATTERY IS LOW
-#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
-#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default
-#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high
-#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high
-#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high
-#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT
-#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT
-#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0
-#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1
- // 00 - REVA
- // 01 - REVB
- // 10 - REVC
- // 11 - REVD
-#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO
-#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active.
- // 0:USB3.0 I/F in Express CARD
- // 1:PCIE I/F in Express CARD detection
-#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF
-#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH#
-#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC
-#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED
-#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted.
-#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ#
-#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ#
-#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK
-#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE
-#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
-#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ#
-#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA
-#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ
-#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1
-#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V
-#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1
-#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT
-#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE
-#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE
-#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE)
- // 1:ENABLE; 0:DISABLE
- // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10
-#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN
-#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER
-#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER
-#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE
-#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ#
-#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700
-#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711
-#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ#
-#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703
-#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM
-#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default
-#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT#
+/* S0-domain General Purpose I/O: GPIO 00~67 */
+#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */
+#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */
+#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */
+#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */
+#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */
+#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */
+#define GPIO_06_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */
+#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */
+#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */
+#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */
+#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */
+#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */
+#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */
+#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, FUNCTION1, Reset_CEC# Low Active, High default */
+#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */
+#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */
+#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */
+#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */
+ /* 1:BATTERY IS FINE(DEFAULT) */
+ /* 0:BATTERY IS LOW */
+#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */
+#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */
+#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */
+#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */
+#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */
+#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */
+#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */
+#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */
+#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */
+ /* 00 - REVA */
+ /* 01 - REVB */
+ /* 10 - REVC */
+ /* 11 - REVD */
+#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */
+#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */
+ /* 0:USB3.0 I/F in Express CARD */
+ /* 1:PCIE I/F in Express CARD detection */
+#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */
+#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */
+#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */
+#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */
+#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */
+#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */
+#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */
+#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */
+#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */
+#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */
+#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */
+#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */
+#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */
+#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */
+#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */
+#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */
+#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */
+#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */
+#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */
+#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */
+ /* 1:ENABLE; 0:DISABLE */
+ /* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */
+#define GPIO_56_SELECT FUNCTION0+NonGpio /* HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */
+#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */
+#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */
+#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */
+#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */
+#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */
+#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */
+#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */
+#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */
+#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */
+#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */
+#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */
#define GPIO_68_SELECT FUNCTION0+NonGpio
#define GPIO_69_SELECT FUNCTION0+NonGpio
#define GPIO_70_SELECT FUNCTION0+NonGpio
@@ -192,40 +192,40 @@
#define GPIO_93_SELECT FUNCTION0+NonGpio
#define GPIO_94_SELECT FUNCTION0+NonGpio
#define GPIO_95_SELECT FUNCTION0+NonGpio
-// GEVENT 00~23 are mapped to GPIO 96~119
-#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0#
-#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1#
-#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP
-#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI#
-#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT#
-#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active
-#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
- // there is a confliction to IR function when this pin is as a GEVENT.
-#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,
- // special pin difination for SB900 VGA OUTPUT, high active,
- // VGA power for Hudson-M2 will be down when it was asserted.
-#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active
-#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio)
-#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2
-#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0
-#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
- // [option for SPI_TPM_CS# in Hudson-M2 A12)]
-#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
- // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
-#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
- // plus judge GPIO40 and GPIO19 level,low is assert.
- // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default)
- // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option)
-#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active
-#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention,
- // low active, when it's low, BIOS will enbale ODD_PWR
-#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17#
-#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK
-#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST#
-#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT
-#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
-#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED#
-#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI
+/* GEVENT 00~23 are mapped to GPIO 96~119 */
+#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */
+#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */
+#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */
+#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */
+#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */
+#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */
+#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */
+ /* there is a confliction to IR function when this pin is as a GEVENT. */
+#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */
+ /* special pin difination for SB900 VGA OUTPUT, high active, */
+ /* VGA power for Hudson-M2 will be down when it was asserted. */
+#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */
+#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */
+#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */
+#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */
+#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */
+ /* [option for SPI_TPM_CS# in Hudson-M2 A12)] */
+#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */
+ /* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */
+#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */
+ /* plus judge GPIO40 and GPIO19 level,low is assert. */
+ /* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */
+ /* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */
+#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */
+#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */
+ /* low active, when it's low, BIOS will enbale ODD_PWR */
+#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */
+#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */
+#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */
+#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */
+#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */
+#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */
+#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */
#define GPIO_120_SELECT FUNCTION0+NonGpio
#define GPIO_121_SELECT FUNCTION0+NonGpio
#define GPIO_122_SELECT FUNCTION0+NonGpio
@@ -268,78 +268,78 @@
#define GPIO_159_SELECT FUNCTION0+NonGpio
#define GPIO_160_SELECT FUNCTION0+NonGpio
-// S5-domain General Purpose I/O
-#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST#
-#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM
-#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2
-#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0
-#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1
-#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2
-#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail.
-#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0,
-#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE
-#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3
-#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT#
-#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_178_SELECT FUNCTION2 // MEM_1V5
-#define GPIO_179_SELECT FUNCTION2 // MEM_1V35
-#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO
-#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR
-#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3
-#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0
-#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB#
-#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB
-#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB
-#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE
-#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE
- // option for HDMI CEC signal OW ACTIVE
-#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active
-#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
-#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA
-#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK
-#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK,
-#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA
-#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK,
-#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA
-#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active
- // RESERVED FOR LCD BACKLIGHT PWM
-#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL
-#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM
-#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF
-#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI
-#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO
-#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO
-#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO
-#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK,
-#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA
-#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
+/* S5-domain General Purpose I/O */
+#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */
+#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */
+#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */
+#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */
+#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */
+#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */
+#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */
+#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */
+#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */
+#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */
+#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */
+#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */
+#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */
+#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */
+#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */
+#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */
+#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */
+#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */
+#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */
+#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */
+#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */
+#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */
+#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */
+#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */
+#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */
+ /* option for HDMI CEC signal OW ACTIVE */
+#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */
+#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */
+#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */
+#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */
+#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */
+#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */
+#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */
+#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */
+#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */
+ /* RESERVED FOR LCD BACKLIGHT PWM */
+#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */
+#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */
+#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */
+#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */
+#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */
+#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */
+#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */
+#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */
+#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */
+#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */
#define TYPE_GPI (1 << 5)
#define TYPE_GPO (0 << 5)
@@ -441,7 +441,7 @@
#define GPIO_94_TYPE TYPE_GPO
#define GPIO_95_TYPE TYPE_GPO
-// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119
+/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */
#define GPIO_96_TYPE TYPE_GPI
#define GPIO_97_TYPE TYPE_GPI
#define GPIO_98_TYPE TYPE_GPI
@@ -753,13 +753,13 @@
#define GPO_169_LEVEL GPO_LOW
#define GPO_170_LEVEL GPO_HI
#define GPO_171_LEVEL GPO_LOW
-#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */
#define GPO_173_LEVEL GPO_LOW
#define GPO_174_LEVEL GPO_LOW
#define GPO_175_LEVEL GPO_LOW
#define GPO_176_LEVEL GPO_LOW
#define GPO_177_LEVEL GPO_LOW
-#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU
+#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */
#define GPO_179_LEVEL GPO_HI
#define GPO_180_LEVEL GPO_HI
#define GPO_181_LEVEL GPO_LOW
@@ -1523,28 +1523,28 @@
#define GEVENT_00_EVENTENABLE EVENT_DISABLE
#define GEVENT_01_EVENTENABLE EVENT_DISABLE
-#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP#
-#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI#
-#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT#
-#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN#
+#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */
+#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */
+#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */
+#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */
#define GEVENT_06_EVENTENABLE EVENT_DISABLE
#define GEVENT_07_EVENTENABLE EVENT_DISABLE
#define GEVENT_08_EVENTENABLE EVENT_DISABLE
-#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO
+#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */
#define GEVENT_10_EVENTENABLE EVENT_DISABLE
#define GEVENT_11_EVENTENABLE EVENT_DISABLE
-#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT#
+#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */
#define GEVENT_13_EVENTENABLE EVENT_DISABLE
-#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK#
-#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN#
-#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA
-#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN
+#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */
+#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */
+#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */
+#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */
#define GEVENT_18_EVENTENABLE EVENT_DISABLE
#define GEVENT_19_EVENTENABLE EVENT_DISABLE
#define GEVENT_20_EVENTENABLE EVENT_DISABLE
#define GEVENT_21_EVENTENABLE EVENT_DISABLE
-#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE#
-#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI#
+#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */
+#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */
#define SCITRIG_LOW 0
#define SCITRIG_HI 1
@@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT
typedef struct _GEVENT_SETTINGS
{
- u8 EventEnable; // 0: Disable, 1: Enable
- u8 SciTrig; // 0: Falling Edge, 1: Rising Edge
- u8 SciLevl; // 0: Edge trigger, 1: Level Trigger
- u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI
- u8 SciS0En; // 0: Disable, 1: Enable
- u8 SciMap; // 0000b->1111b
- u8 SmiTrig; // 0: Active Low, 1: Active High
- u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13
+ u8 EventEnable; /* 0: Disable, 1: Enable */
+ u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */
+ u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */
+ u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */
+ u8 SciS0En; /* 0: Disable, 1: Enable */
+ u8 SciMap; /* 0000b->1111b */
+ u8 SmiTrig; /* 0: Active Low, 1: Active High */
+ u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */
} GEVENT_SETTINGS;
const GEVENT_SETTINGS gevent_table[] =
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 86339ef..9bd9088 100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -22,7 +22,6 @@
#include <device/pci_def.h>
#define ONE_MB 0x100000
-//#define SMBUS_IO_BASE 0x6000
void set_pcie_reset(void);
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 8091ffb..8aeb250 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
@@ -95,7 +94,6 @@ static void *smp_write_config_table(void *v)
cpu_flag, cpu_features, cpu_feature_flags
);
- //mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
@@ -130,7 +128,6 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1);
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index 0713e41..5009607 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_
@@ -98,30 +97,19 @@
/**
* @section Smbus0BaseAddress
*/
-// #ifndef SMBUS0_BASE_ADDRESS
-// #define SMBUS0_BASE_ADDRESS 0xB00
-// #endif
/**
* @section Smbus1BaseAddress
*/
-// #ifndef SMBUS1_BASE_ADDRESS
-// #define SMBUS1_BASE_ADDRESS 0xB21
-// #endif
/**
* @section SioPmeBaseAddress
*/
-// #ifndef SIO_PME_BASE_ADDRESS
-// #define SIO_PME_BASE_ADDRESS 0xE00
-// #endif
/**
* @section WatchDogTimerBase
*/
-// #ifndef WATCHDOG_TIMER_BASE_ADDRESS
-// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR
-// #endif
+
/**
* @section GecShadowRomAddress
@@ -133,58 +121,39 @@
/**
* @section SpiRomBaseAddress
*/
-// #ifndef SPI_BASE_ADDRESS
-// #define SPI_BASE_ADDRESS 0xFEC10000
-// #endif
/**
* @section AcpiPm1EvtBlkAddr
*/
-// #ifndef PM1_EVT_BLK_ADDRESS
-// #define PM1_EVT_BLK_ADDRESS 0x400
-// #endif
/**
* @section AcpiPm1CntBlkAddr
*/
-// #ifndef PM1_CNT_BLK_ADDRESS
-// #define PM1_CNT_BLK_ADDRESS 0x404
-// #endif
+
/**
* @section AcpiPmTmrBlkAddr
*/
-// #ifndef PM1_TMR_BLK_ADDRESS
-// #define PM1_TMR_BLK_ADDRESS 0x408
-// #endif
+
/**
* @section CpuControlBlkAddr
*/
-// #ifndef CPU_CNT_BLK_ADDRESS
-// #define CPU_CNT_BLK_ADDRESS 0x410
-// #endif
+
/**
* @section AcpiGpe0BlkAddr
*/
-// #ifndef GPE0_BLK_ADDRESS
-// #define GPE0_BLK_ADDRESS 0x420
-// #endif
+
/**
* @section SmiCmdPortAddr
*/
-// #ifndef SMI_CMD_PORT
-// #define SMI_CMD_PORT 0xB0
-// #endif
/**
* @section AcpiPmaCntBlkAddr
*/
-// #ifndef ACPI_PMA_CNT_BLK_ADDRESS
-// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
-// #endif
+
/**
* @section InChipSataController
@@ -1192,7 +1161,7 @@
#define INCHIP_STRESS_RESET_MODE 0
#ifndef SB_PCI_CLOCK_RESERVED
- #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F
+ #define SB_PCI_CLOCK_RESERVED 0x0 /* according to CIMx change 0x1F */
#endif
/**
@@ -1214,7 +1183,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg);
*/
u32 sb900_callout_entry(u32 func, u32 data, void* config);
-// definition for function in gpio.c
+/* definition for function in gpio.c */
void gpioEarlyInit (void);
#endif
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 74402bf..e8395fa 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x34);
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
@@ -87,5 +87,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run returned!\n");
- post_code(0x44); // Should never see this post code.
+ post_code(0x44); /* Should never see this post code. */
}
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