[coreboot-gerrit] New patch to review for coreboot: mainboard/amd/union_station: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 10 21:47:13 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16980
-gerrit
commit 9046a943b743f465c4d4831bc2701d27828866be
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 10 21:45:26 2016 +0200
mainboard/amd/union_station: Use C89 comments style & remove commented code
Change-Id: Ifcb8fadbbb2a21df6c8fbb365374b45ca288f6a2
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/union_station/BiosCallOuts.c | 26 ++---
src/mainboard/amd/union_station/OemCustomize.c | 25 +++--
src/mainboard/amd/union_station/OptionsIds.h | 8 --
.../amd/union_station/PlatformGnbPcieComplex.h | 72 +++++++-------
src/mainboard/amd/union_station/buildOpts.c | 108 +++++----------------
src/mainboard/amd/union_station/mptable.c | 3 +-
src/mainboard/amd/union_station/platform_cfg.h | 1 -
7 files changed, 87 insertions(+), 156 deletions(-)
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index bc28086..71af45a 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
- // Get SB800 MMIO Base (AcpiMmioAddr)
+ /* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
@@ -152,14 +152,14 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */
Status = AGESA_SUCCESS;
break;
}
@@ -169,14 +169,14 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */
Status = AGESA_SUCCESS;
break;
}
@@ -186,14 +186,14 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
+ Data8 &= ~(UINT8)BIT6 ;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
+ Data8 |= BIT6 ;
+ Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */
Status = AGESA_SUCCESS;
break;
}
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 6f4dbfc..5378e2d 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -52,33 +52,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = {
- // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
},
#if 1
- // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
},
- // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
},
- // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
},
#endif
- // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+ /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
@@ -87,18 +87,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
- // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+ /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */
{ConnectorTypeHDMI, Aux1, Hdp1}
},
- // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+ /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */
{ConnectorTypeHDMI, Aux2, Hdp2}
}
};
@@ -110,11 +110,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
&DdiList[0]
};
- // GNB PCIe topology Porting
+ /* GNB PCIe topology Porting */
+
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
- //
- // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
- //
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h
index 2d8381b..7a9c03f 100644
--- a/src/mainboard/amd/union_station/OptionsIds.h
+++ b/src/mainboard/amd/union_station/OptionsIds.h
@@ -43,14 +43,6 @@
**/
#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
-
#endif
diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
index 001ed16..0e0255e 100644
--- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
@@ -20,45 +20,45 @@
#include "AGESA.h"
#include "amdlib.h"
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port4 */
+#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port5 */
+#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port6 */
+#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port7 */
+#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/* GNB GPP Port8 */
+#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */
+#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */
+#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */
+ /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
+#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 38a272d..648212c 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -29,7 +29,6 @@
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
@@ -74,7 +73,6 @@
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
@@ -94,10 +92,7 @@
#define BLDOPT_REMOVE_DMI TRUE
#define BLDOPT_REMOVE_HT_ASSIST TRUE
#define BLDOPT_REMOVE_ATM_MODE TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
-//#define BLDOPT_REMOVE_C6_STATE TRUE
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
@@ -106,65 +101,23 @@
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
#define BLDCFG_VRM_CURRENT_LIMIT 24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
#define BLDCFG_VRM_SLEW_RATE 5000
-//#define BLDCFG_VRM_NB_SLEW_RATE 5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY 0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
#define BLDCFG_PLAT_NUM_IO_APICS 3
-//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA 0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
-//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM 0
-//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
-//#define BLDCFG_BUID_SWAP_LIST 0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
-//#define BLDCFG_BUS_NUMBERS_LIST 0
-//#define BLDCFG_IGNORE_LINK_LIST 0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
-//#define BLDCFG_USE_HT_ASSIST TRUE
-//#define BLDCFG_USE_ATM_MODE TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
#define BLDCFG_S3_LATE_RESTORE FALSE
-//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_CFG_ABM_SUPPORT FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
-//#define BLDCFG_MEM_INIT_PSTATE 0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
@@ -172,8 +125,6 @@
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
#define BLDCFG_MEMORY_POWER_DOWN TRUE
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
@@ -181,16 +132,6 @@
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
-//#define BLDCFG_ECC_REDIRECTION FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE 0
-//#define BLDCFG_SCRUB_L2_RATE 0
-//#define BLDCFG_SCRUB_L3_RATE 0
-//#define BLDCFG_SCRUB_IC_RATE 0
-//#define BLDCFG_SCRUB_DC_RATE 0
-//#define BLDCFG_ECC_SYNC_FLOOD 0
-//#define BLDCFG_ECC_SYMBOL_SIZE 0
-//#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
#define BLDCFG_UMA_ALLOCATION_SIZE 0
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
@@ -249,41 +190,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 /* DDR 400 */
+#define DDR533_FREQUENCY 266 /* DDR 533 */
+#define DDR667_FREQUENCY 333 /* DDR 667 */
+#define DDR800_FREQUENCY 400 /* DDR 800 */
+#define DDR1066_FREQUENCY 533 /* DDR 1066 */
+#define DDR1333_FREQUENCY 667 /* DDR 1333 */
+#define DDR1600_FREQUENCY 800 /* DDR 1600 */
+#define DDR1866_FREQUENCY 933 /* DDR 1866 */
+#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 /* Use best rate possible */
+#define TIMING_MODE_LIMITED 1 /* Set user top limit */
+#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
@@ -292,5 +234,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data. */
#include "PlatformInstall.h"
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index c24e42c..87572c5 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
@@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+ /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h
index d39a3ab..4e6adb1 100644
--- a/src/mainboard/amd/union_station/platform_cfg.h
+++ b/src/mainboard/amd/union_station/platform_cfg.h
@@ -161,7 +161,6 @@
* SDIN2 is define at BIT4 & BIT5
* SDIN3 is define at BIT6 & BIT7
*/
-//#define AZALIA_SDIN_PIN 0xAA
#define AZALIA_SDIN_PIN 0x2A
/**
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