[coreboot-gerrit] New patch to review for coreboot: arch/riscv: In trap handler, don't print SP twice

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16996

-gerrit

commit f8b7e64a31116d81e83f7c4dfbeeb10a4fe0b41c
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Wed Oct 12 00:18:02 2016 +0200

    arch/riscv: In trap handler, don't print SP twice
    
    The stack pointer (SP) is already printed in print_trap_information.
    Don't print it again in handle_misaligned_{load,store}.
    
    Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/arch/riscv/trap_handler.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 59aa221..ad49928 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -173,7 +173,6 @@ static uint32_t fetch_instruction(uintptr_t vaddr) {
 
 void handle_misaligned_load(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr:      %p\n", tf);
-	printk(BIOS_DEBUG, "Stored sp:          %p\n", (void*) tf->gpr[2]);
 	uintptr_t faultingInstructionAddr = tf->epc;
 	insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
 	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
@@ -203,7 +202,6 @@ void handle_misaligned_load(trapframe *tf) {
 
 void handle_misaligned_store(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr:      %p\n", tf);
-	printk(BIOS_DEBUG, "Stored sp:          %p\n", (void*) tf->gpr[2]);
 	uintptr_t faultingInstructionAddr = tf->epc;
 	insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
 	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);