[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Set PL1 limits for RAPL MSR registers

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a247d8e53cebbd754e46f76412ed9d17df752308
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Tue Sep 27 23:18:35 2016 +0530

    soc/intel/apollolake: Set PL1 limits for RAPL MSR registers
    
    This patch sets the package power limit (PL1) value in RAPL MSR
    and disables MMIO register. Added configurable PL1 override
    parameter to leverage full TDP capacity.
    
    BUG=chrome-os-partner:56922
    TEST=webGL performance(fps) not impacted before and after S3.
    
    Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    Reviewed-on: https://review.coreboot.org/16884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/16884 for details.

-gerrit