[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Handle platform global reset

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 9a20551b7e15ff8bb05922489ee4649f1b7f4826
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Aug 19 13:17:36 2016 +0530

    soc/intel/skylake: Handle platform global reset
    
    In FSP1.1 all the platform resets including global was handled
    on its own without any intervention from coreboot.
    In FSP2.0, any reset required will be notified to coreboot
    and it is expected that coreboot will perform platform reset.
    
    Hence, implement platform global reset hooks in coreboot. If Intel
    ME is in non ERROR state then MEI message will able to perform
    global reset else force global reset by writing 0x6 or 0xE to
    0xCF9 port with PCH ETR3 register bit [20] set.
    
    BUG=none
    BRANCH=none
    TEST=Verified platform global reset is working with MEI
    message or writing to PCH ETR3.
    
    Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Reviewed-on: https://review.coreboot.org/16903
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/16903 for details.

-gerrit