[coreboot-gerrit] New patch to review for coreboot: Skylake: Add _ACx methods for TSR0 sensor for fan control

[Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com)]

Sumeet R Pawnikar (sumeet.r.pawnikar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17067

-gerrit

commit ecb6a9354b74506eeea3c56b804ea43c2e007d04
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Tue Oct 18 10:57:58 2016 +0530

    Skylake: Add _ACx methods for TSR0 sensor for fan control
    
    This patch adds the _ACx methods for other external sensor
    TSR0 for Fan speed control on Skylake-U based Kunimitsu and
    Lars boards.
    
    BUG=chrome-os-partner:51025
    BRANCH=firmware-glados-7820.B
    TEST=Built and booted on kunimitsu and lars EVT boards.
    Verified these _ACx methods with _ART table on these boards
    with different workloads.
    
    Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
    Reviewed-on: https://chromium-review.googlesource.com/332368
---
 src/soc/intel/skylake/acpi/dptf/cpu.asl     | 20 ----------------
 src/soc/intel/skylake/acpi/dptf/thermal.asl | 37 +++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 20 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl
index 32e8863..6278b9f 100644
--- a/src/soc/intel/skylake/acpi/dptf/cpu.asl
+++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl
@@ -22,26 +22,6 @@
 #define DPTF_CPU_CRITICAL       90
 #endif
 
-#ifndef DPTF_CPU_ACTIVE_AC0
-#define DPTF_CPU_ACTIVE_AC0     90
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC1
-#define DPTF_CPU_ACTIVE_AC1     80
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC2
-#define DPTF_CPU_ACTIVE_AC2     70
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC3
-#define DPTF_CPU_ACTIVE_AC3     60
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC4
-#define DPTF_CPU_ACTIVE_AC4     50
-#endif
-
 External (\_PR.CP00._PSS, PkgObj)
 External (\_PR.CP00._TSS, PkgObj)
 External (\_PR.CP00._TPC, MethodObj)
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index 97484e5..a171eb1 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -111,6 +111,43 @@ Device (TSR0)
 	{
 		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
 	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+	Method (_AC0)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+	}
+
+	Method (_AC1)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+	}
+
+	Method (_AC2)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+	}
+
+	Method (_AC3)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+	}
+
+	Method (_AC4)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+	}
+
+	Method (_AC5)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+	}
+
+	Method (_AC6)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+	}
+#endif
 }
 #endif