[coreboot-gerrit] New patch to review for coreboot: Lars: Update DPTF settings

[Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com)]

Sumeet R Pawnikar (sumeet.r.pawnikar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17068

-gerrit

commit 1dc8ea89667beb56261009a4a8b6ef6774064a27
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Tue Oct 18 11:07:39 2016 +0530

    Lars: Update DPTF settings
    
    This patch updates few DPTF settings.
    
    BUG=chrome-os-partner:51025
    BRANCH=firmware-glados-7820.B
    TEST=Built and booted on lars DVT boards. Verified these
    updated DPTF settings with different workloads.
    
    Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
    Reviewed-on: https://chromium-review.googlesource.com/338877
---
 src/mainboard/google/lars/acpi/dptf.asl | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl
index b8f0a7a..82a23f8 100644
--- a/src/mainboard/google/lars/acpi/dptf.asl
+++ b/src/mainboard/google/lars/acpi/dptf.asl
@@ -14,15 +14,15 @@
  * GNU General Public License for more details.
  */
 
-#define DPTF_CPU_PASSIVE	95
+#define DPTF_CPU_PASSIVE	94
 #define DPTF_CPU_CRITICAL       99
 #define DPTF_CPU_ACTIVE_AC0     90
 #define DPTF_CPU_ACTIVE_AC1	77
 
 #define DPTF_TSR0_SENSOR_ID	0
 #define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
-#define DPTF_TSR0_PASSIVE	65
-#define DPTF_TSR0_CRITICAL	70
+#define DPTF_TSR0_PASSIVE	66
+#define DPTF_TSR0_CRITICAL	71
 #define DPTF_TSR0_ACTIVE_AC0	120
 #define DPTF_TSR0_ACTIVE_AC1	110
 #define DPTF_TSR0_ACTIVE_AC2	47
@@ -33,13 +33,13 @@
 
 #define DPTF_TSR1_SENSOR_ID	1
 #define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE	63
-#define DPTF_TSR1_CRITICAL	68
+#define DPTF_TSR1_PASSIVE	75
+#define DPTF_TSR1_CRITICAL	80
 
 #define DPTF_TSR2_SENSOR_ID	2
 #define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE	64
-#define DPTF_TSR2_CRITICAL	69
+#define DPTF_TSR2_PASSIVE	65
+#define DPTF_TSR2_CRITICAL	70
 
 #define DPTF_ENABLE_CHARGER
 #define DPTF_ENABLE_FAN_CONTROL
@@ -83,12 +83,12 @@ Name (DART, Package () {
 		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
 		 *	AC7, AC8, AC9
 		 */
-		\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0,
+		\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0,
 			0, 0, 0
 	},
 	Package () {
-		\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40,
-			35, 0, 0, 0
+		\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38,
+			37, 0, 0, 0
 	}
 })
 #endif