[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17181

-gerrit

commit e30a6db3a991d003517575f3e5b1f3124f94b7cc
Author: Lijian Zhao <lijian.zhao at intel.com>
Date:   Fri Oct 28 11:01:09 2016 -0700

    soc/intel/apollolake: Add pmc_ipc device support
    
    A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
    The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
    Punit Mailbox. Also optimize the asl sequence to have SB.PCI0 blocks
    together.
    
    BRANCH=None
    BUG=chrome-os-partner:57364
    TEST=Boot up into OS successfully and check with dmesg to see the
    driver has been loaded successfully without errors.
    
    Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1
    Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
 src/soc/intel/apollolake/acpi/pmc_ipc.asl     | 61 +++++++++++++++++++++++++++
 src/soc/intel/apollolake/acpi/southbridge.asl |  9 ++--
 2 files changed, 67 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..d5c1ceb
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+scope (\_SB) {
+
+	Device (IPC1)
+	{
+		Name (_HID, "INT34D2")
+		Name (_CID, "INT34D2")
+		Name (_DDN, "Intel(R) IPC1 Controller")
+		Name (RBUF, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
+			Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
+			Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
+			IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE + PMIO_LENGTH,
+			      0x04, PMIO_LENGTH)
+			Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+			{
+			      PMC_INT
+			}
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+			Store (PMC_BAR0, IBAS)
+
+			CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+			Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA)
+			CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+			Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA)
+
+			CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+			Store (PMC_SRAM_BASE_0, SBAS)
+
+			Return (^RBUF)
+		}
+	}
+
+}
\ No newline at end of file
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 1c10f1a..225bc48 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -35,9 +35,6 @@ Scope (\_SB)
 /* PCI IRQ assignment */
 #include "pci_irqs.asl"
 
-/* GPIO controller */
-#include "gpio.asl"
-
 #include "xhci.asl"
 
 /* LPC */
@@ -46,5 +43,11 @@ Scope (\_SB)
 /* eMMC */
 #include "scs.asl"
 
+/* GPIO controller */
+#include "gpio.asl"
+
+/* PMC IPC controller */
+#include "pmc_ipc.asl"
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>