[coreboot-gerrit] New patch to review for coreboot: southbridge/amd/sb600: transition away from device_t

[Antonello Dettori (dev@dettori.io)]

Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16478

-gerrit

commit d841e559a1febb861204ae9c6722a9ecc6001af8
Author: Antonello Dettori <dev at dettori.io>
Date:   Sat Sep 3 10:45:33 2016 +0200

    southbridge/amd/sb600: transition away from device_t
    
    Replace the use of the old device_t definition inside
    southbridge/amd/sb600.
    
    Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39
    Signed-off-by: Antonello Dettori <dev at dettori.io>
---
 src/southbridge/amd/sb600/early_setup.c | 14 +++++++-------
 src/southbridge/amd/sb600/sb600.h       |  4 +++-
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index cbe8b0c..2caa28b 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -36,7 +36,7 @@ static u8 pmio_read(u8 reg)
 /* RPR 2.1: Get SB ASIC Revision. */
 static u8 get_sb600_revision(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 
 	if (dev == PCI_DEV_INVALID) {
@@ -63,7 +63,7 @@ static void sb600_lpc_init(void)
 {
 	u8 reg8;
 	u32 reg32;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);	/* SMBUS controller */
 	/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
@@ -102,7 +102,7 @@ static void sb600_lpc_init(void)
 /* what is its usage? */
 static u32 get_sbdn(u32 bus)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	/* Find the device. */
 	dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
@@ -192,7 +192,7 @@ void soft_reset(void)
 void sb600_pci_port80(void)
 {
 	u8 byte;
-	device_t dev;
+	pci_devfn_t dev;
 
 	/* P2P Bridge */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -237,7 +237,7 @@ void sb600_pci_port80(void)
 void sb600_lpc_port80(void)
 {
 	u8 byte;
-	device_t dev;
+	pci_devfn_t dev;
 	u32 reg32;
 
 	/* Enable LPC controller */
@@ -256,7 +256,7 @@ void sb600_lpc_port80(void)
 /* sbDevicesPorInitTable */
 static void sb600_devices_por_init(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	u8 byte;
 
 	printk(BIOS_INFO, "sb600_devices_por_init()\n");
@@ -516,7 +516,7 @@ static void sb600_pmio_por_init(void)
 */
 static void sb600_pci_cfg(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	u8 byte;
 
 	/* SMBus Device, BDF:0-20-0 */
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 5c1111a..94ee861 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -34,9 +34,11 @@ extern void pm_iowrite(u8 reg, u8 value);
 extern u8 pm_ioread(u8 reg);
 extern void pm2_iowrite(u8 reg, u8 value);
 extern u8 pm2_ioread(u8 reg);
-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
 
+#ifndef __SIMPLE_DEVICE__
+extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
 void sb600_enable(device_t dev);
+#endif
 
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);