[coreboot-gerrit] New patch to review for coreboot: southbridge/amd/sb700: transition away from device_t

[Antonello Dettori (dev@dettori.io)]

Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16479

-gerrit

commit 9752ad5761dca6007df0010b4031050380461cae
Author: Antonello Dettori <dev at dettori.io>
Date:   Sat Sep 3 10:45:33 2016 +0200

    southbridge/amd/sb700: transition away from device_t
    
    Replace the use of the old device_t definition inside
    southbridge/amd/sb700.
    
    Change-Id: I44b0be2070719066dd18bbf2882c417caef5d8b2
    Signed-off-by: Antonello Dettori <dev at dettori.io>
---
 src/southbridge/amd/sb700/early_setup.c | 18 +++++++++---------
 src/southbridge/amd/sb700/sb700.h       |  4 ++++
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 755a161..1aa7be0 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -77,7 +77,7 @@ static void sb700_acpi_init(void)
 /* RPR 2.28: Get SB ASIC Revision. */
 static u8 set_sb700_revision(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	u8 rev_id, enable_14Mhz, byte;
 	u8 rev = 0;
 
@@ -134,7 +134,7 @@ void sb7xx_51xx_lpc_init(void)
 {
 	u8 reg8;
 	u32 reg32;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);	/* SMBUS controller */
 	/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
@@ -193,7 +193,7 @@ void sb7xx_51xx_lpc_init(void)
 void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
 {
 	/* TODO: Now assume wio_index=0 */
-	device_t dev;
+	pci_devfn_t dev;
 	u8 reg8;
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
@@ -206,7 +206,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
 void sb7xx_51xx_disable_wideio(u8 wio_index)
 {
 	/* TODO: Now assume wio_index=0 */
-	device_t dev;
+	pci_devfn_t dev;
 	u8 reg8;
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
@@ -219,7 +219,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index)
 /* what is its usage? */
 u32 get_sbdn(u32 bus)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	/* Find the device. */
 	dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
@@ -284,7 +284,7 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 void sb7xx_51xx_pci_port80(void)
 {
 	u8 byte;
-	device_t dev;
+	pci_devfn_t dev;
 
 	/* P2P Bridge */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -329,7 +329,7 @@ void sb7xx_51xx_pci_port80(void)
 void sb7xx_51xx_lpc_port80(void)
 {
 	u8 byte;
-	device_t dev;
+	pci_devfn_t dev;
 	u32 reg32;
 
 	/* Enable LPC controller */
@@ -348,7 +348,7 @@ void sb7xx_51xx_lpc_port80(void)
 /* sbDevicesPorInitTable */
 static void sb700_devices_por_init(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	u8 byte;
 	uint32_t dword;
 	uint8_t nvram;
@@ -705,7 +705,7 @@ static void sb700_pmio_por_init(void)
 */
 static void sb700_pci_cfg(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	u8 byte;
 	uint8_t acpi_s1_supported = 1;
 
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index f23956c..191dff1 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -42,7 +42,9 @@ extern void pm_iowrite(u8 reg, u8 value);
 extern u8 pm_ioread(u8 reg);
 extern void pm2_iowrite(u8 reg, u8 value);
 extern u8 pm2_ioread(u8 reg);
+#ifndef __SIMPLE_DEVICE__
 extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
+#endif
 
 #define REV_SB700_A11	0x11
 #define REV_SB700_A12	0x12
@@ -56,7 +58,9 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
  * The differentiate is 0x28, isn't it? */
 #define get_sb700_revision(sm_dev)	(pci_read_config8((sm_dev), 0x08) - 0x28)
 
+#ifndef __SIMPLE_DEVICE__
 void sb7xx_51xx_enable(device_t dev);
+#endif
 
 #ifdef __PRE_RAM__
 void sb7xx_51xx_lpc_port80(void);