[coreboot-gerrit] Patch set updated for coreboot: cpu/amd/model_fxx: transition away from device_t

[Antonello Dettori (dev@dettori.io)]

Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16437

-gerrit

commit 650c54cb12ae37bca66a92363b974c966b44f057
Author: Antonello Dettori <dev at dettori.io>
Date:   Sat Sep 3 10:45:33 2016 +0200

    cpu/amd/model_fxx: transition away from device_t
    
    Replace the use of the old device_t definition inside
    cpu/amd/model_fxx.
    
    Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0
    Signed-off-by: Antonello Dettori <dev at dettori.io>
---
 src/cpu/amd/model_fxx/init_cpus.c   |  2 +-
 src/include/cpu/amd/model_fxx_rev.h | 41 +++++++++++++++++++------------------
 2 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 63c8823..d38c552 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -342,7 +342,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 static u32 is_core0_started(u32 nodeid)
 {
 	u32 htic;
-	device_t device;
+	pci_devfn_t device;
 	device = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(device, HT_INIT_CONTROL);
 	htic &= HTIC_INIT_Detect;
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index be961f2..88945a2 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -73,29 +73,29 @@ static inline int is_e0_later_in_bsp(int nodeid)
 	if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
 		return 1;
 
-	if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0
-		return !is_cpu_pre_e0();
-	}
-	// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
-	device_t dev;
-	dev = PCI_DEV(0, 0x18+nodeid,2);
-	val_old = pci_read_config32(dev, 0x80);
-	val = val_old;
-	val |= (1<<3);
-	pci_write_config32(dev, 0x80, val);
-	val = pci_read_config32(dev, 0x80);
-	e0_later = !!(val & (1<<3));
-	if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
-		pci_write_config32(dev, 0x80, val_old); // restore it
-	}
-
-	return e0_later;
+        if (nodeid==0) { // we don't need to do that for node 0 in core0/node0
+                return !is_cpu_pre_e0();
+        }
+        // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
+	pci_devfn_t dev;
+        dev = PCI_DEV(0, 0x18+nodeid,2);
+        val_old = pci_read_config32(dev, 0x80);
+        val = val_old;
+        val |= (1<<3);
+        pci_write_config32(dev, 0x80, val);
+        val = pci_read_config32(dev, 0x80);
+        e0_later = !!(val & (1<<3));
+        if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
+                pci_write_config32(dev, 0x80, val_old); // restore it
+        }
+
+        return e0_later;
 }
 
 static inline int is_cpu_f0_in_bsp(int nodeid)
 {
 	uint32_t dword;
-	device_t dev;
+	pci_devfn_t dev;
 	if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
 		return 0;
 	dev = PCI_DEV(0, 0x18+nodeid, 3);
@@ -105,8 +105,9 @@ static inline int is_cpu_f0_in_bsp(int nodeid)
 
 static inline int is_cpu_pre_f2_in_bsp(int nodeid)
 {
-	uint32_t dword;
-	device_t dev;
+        uint32_t dword;
+	pci_devfn_t dev;
+
 	if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
 		return 1;
 	dev = PCI_DEV(0, 0x18+nodeid, 3);