[coreboot] patch: dbe62

[ron minnich]

On Thu, Feb 28, 2008 at 5:00 PM, Peter Stuge <peter at stuge.se> wrote:

>  > +     help
>  > +       This is the default mainboard name.
>
>  What's a default name?

you'll have to ask the guy who wrote that Kconfig file. I'm just a
humble intern.



>  > +     /*
>  > +      * NOTE: Must do this AFTER the early_setup! It is counting on some
>  > +      * early MSR setup for the CS5536.
>  > +      */
>  > +     cs5536_setup_onchipuart();
>  > +}
>
>  What early_setup?! Please fix this comment in all boards before it
>  is copypasted again. I'll do it if someone tells me where this early
>  MSR setup is done now. dbe62_msr_init() ?

yes. Unlike just about any other board, due to the way this chipset
works, the onchip uart is not independent in ways we are used to.
Comment away!

>  > +void mainboard_pre_payload(void)
>  > +{
>  > +     geode_pre_payload();
>  > +     banner(BIOS_DEBUG, "mainboard_pre_payload: done");
>  > +}
>
>  Why do we need this mainboard code when it is only calling a
>  function that can be determined using the dts?

Show me how. I don't know.

>  > +unsigned long write_pirq_routing_table(unsigned long addr)
>
>  What an abomination. hint hint ;)
>
>  Can this code really not live in northbridge/ ?

no, it's a south function, with mainboard-dependent bits. I'm happy to
see a way to make it generic, I just don't know how yet.

>  > +                     /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
>  > +                     lpc_serirq_polarity = "0x0000EFFD";
>  > +                     /* 0:continuous 1:quiet */
>  > +                     lpc_serirq_mode = "1";
>  > +                     /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
>  > +                      * See virtual PIC spec. */
>  > +                     enable_gpio_int_route = "0x0D0C0700";
>
>  Yes! So completely on track. :)

are you happy or unhappy here? Just want to make sure ...

ron