[coreboot] [PATCH] [RFC] v3: CS5536 cleanup

[Carl-Daniel Hailfinger]

Clean up Geode companion chip CS5536 code and improve VPCI hiding
debug message. This also eliminates a few dev_find_pci_device().

I'm not happy with the new code yet. hide_vpci() should have a
variant which takes a struct device *.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c	(Revision 676)
+++ LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c	(Arbeitskopie)
@@ -175,8 +175,7 @@
 static void enable_ide_nand_flash_header(void)
 {
 	/* Tell VSA to use FLASH PCI header. Not IDE header. */
-	outl(0x80007A40, 0xCF8);
-	outl(0xDEADBEEF, 0xCFC);
+	hide_vpci(0x800079C4);
 }
 
 #define RTC_CENTURY	0x32
@@ -240,16 +239,13 @@
  *
  * @param sb Southbridge config structure.
  */
-static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
+static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb,
+			struct device *dev)
 {
 	struct msr msr;
 	u16 addr = 0;
 	u32 gpio_addr;
-	struct device *dev;
 
-	dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
-			      PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
-
 	gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 	gpio_addr &= ~1;	/* Clear I/O bit */
 	printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
@@ -418,7 +414,7 @@
 {
 	u32 *bar;
 	struct msr msr;
-	struct device *dev;
+	struct device *dev, *otg_dev;
 
 	dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
 			      PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
@@ -440,9 +436,9 @@
 		*(bar + HCCPARAMS) = 0x00005012;
 	}
 
-	dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
+	otg_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
 			      PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
-	if (dev) {
+	if (otg_dev) {
 		bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
 		*(bar + UOCMUX) &= PUEN_SET;
@@ -472,9 +468,7 @@
 			*(bar + UDCDEVCTL) |= UDC_SD_SET;
 		}
 
-		dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
-				      PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
-		if (dev) {
+		if (otg_dev) {
 			bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			*(bar + UOCCTL) |= PADEN_SET;
 			*(bar + UOCCAP) |= APU_SET;
@@ -482,15 +476,8 @@
 	}
 
 	/* Disable virtual PCI UDC and OTG headers. */
-	dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
-			      PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
-	if (dev)
-		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
-
-	dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
-			      PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
-	if (dev)
-		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
+	hide_vpci(0x80007e00); /* UDC */
+	hide_vpci(0x80007f00); /* OTG */
 }
 
 /** 
@@ -603,9 +590,19 @@
 
 static void hide_vpci(u32 vpci_devid)
 {
-	/* Hide unwanted virtual PCI device. */
-	printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X\n",
-		vpci_devid);
+	/* Hide unwanted virtual PCI device.
+	 * bits  0 ->  1 zero
+	 * bits  2 ->  7 target dword within the target function 
+	 *               (zero if we're disabling entire pci devices)
+	 * bits  8 -> 10 target function of the device
+	 * bits 11 -> 15 target pci device
+	 * bits 16 -> 23 pci bus
+	 * bits 24 -> 30 reserved and set to zero
+	 * bit  31       triggers the config cycle
+	 */
+	printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n",
+		vpci_devid, (vpci_devid >> 16) & 0xff,
+		(vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7);
 	outl(vpci_devid + 0x7C, 0xCF8);
 	outl(0xDEADBEEF, 0xCFC);
 }
@@ -630,7 +627,7 @@
 
 	setup_i8259();
 	lpc_init(sb);
-	uarts_init(sb);
+	uarts_init(sb, dev);
 
 	if (sb->enable_gpio_int_route) {
 		printk(BIOS_SPEW, "cs5536: call vr_write\n");