[coreboot] fam10/newconfig on supermicro h8dme - early hang
ward at gnu.org
Wed Dec 23 02:36:31 CET 2009
On Tue, Dec 22, 2009 at 04:11:06PM -0700, Myles Watson wrote:
> > Right. Setting CONFIG_LOGICAL_CPUS to zero and making sure that
> > conditional
> > on CONFIG_LOGICAL_CPUS at the top of northbridge.c does not apply fixed
> > that.
> > Should this go into the tree?
> > --- northbridge/amd/amdfam10/northbridge.c (revision 4978)
> > +++ northbridge/amd/amdfam10/northbridge.c (working copy)
> > @@ -31,10 +31,10 @@
> > #include <cpu/x86/lapic.h>
> > -#if CONFIG_LOGICAL_CPUS==1
> > #include <cpu/amd/quadcore.h>
> > #include <pc80/mc146818rtc.h>
> > -#endif
> > #include "chip.h"
> > #include "root_complex/chip.h"
> I like just moving the endif to protect nb_cfg_54, if it would work. It
> compiles for me.
> --- northbridge/amd/amdfam10/northbridge.c (revision 4978)
> +++ northbridge/amd/amdfam10/northbridge.c (working copy)
> @@ -1235,7 +1235,6 @@
> disable_siblings = !CONFIG_LOGICAL_CPUS;
> #if CONFIG_LOGICAL_CPUS == 1
> get_option(&disable_siblings, "quad_core");
> // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read
> // still be 0)
> @@ -1243,6 +1242,7 @@
> // and differ d0 and e0 single core
> nb_cfg_54 = read_nb_cfg_54();
> #if CONFIG_CBB
> dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
OK - with that patch it builds and boots, and the output looks similar (but
not identical. See
The only difference is this
-MMIO(b8)0000000000-31a4f2ffff, ->(0,1), , , CPU disable 0, Lock 0, Non
+MMIO(b8)0000000000-31a6b2ffff, ->(0,1), , , CPU disable 0, Lock 0, Non
which may be entirely unrelated?
I'll look at that other register tomorrow.
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator
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