[coreboot] [Mohon Peak] Console output on external UARTs behind PCIe

[Patrick Agrain]

Hi,

More information on this.

The POST code sequence (as far I can see, but I'm not Steeve Austin...) is:
40h -> 47h -> A9h

IMHO, we are parsing following code from 
./src/southbridge/intel/fsp_rangeley/romstage.c
void main(FSP_INFO_HEADER *fsp_info_header)
{
     uint32_t fd_mask = 0;
     uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;

     /*
      * Do not use the Serial Console before it is setup.
      * This causes the I/O to clog and a side effect is
      * that the reset button stops functioning.  So
      * instead just use outb so it doesn't output to the
      * console when CONFIG_CONSOLE_POST.
      */
     outb(0x40, 0x80);

     /* Rangeley UART POR state is enabled */
     console_init();
     post_code(0x41);

     /* Enable GPIOs BAR */
     pci_write_config32(SOC_LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02);

     early_mainboard_romstage_entry();

     post_code(0x42);
     rangeley_sb_early_initialization();

     post_code(0x46);
     /* Program any required function disables */
     get_func_disables(&fd_mask);

     if (fd_mask != 0) {
         write32(func_dis, read32(func_dis) | fd_mask);
         /* Ensure posted write hits. */
         read32(func_dis);
     }

   /*
    * Call early init to initialize memory and chipset. This function 
returns
    * to the romstage_main_continue function with a pointer to the HOB
    * structure.
    */
     post_code(0x47);
     printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
     fsp_early_init(fsp_info_header);
     die("Uh Oh! fsp_early_init should not return here.\n");
}

... and I'm affraid we get stucked in the fsp_early_init() function ... :-(

Regards.
Patrick Agrain

Le 11/03/2015 16:21, Patrick Agrain a écrit :
> Hello Kyösti,
>
> I tried what you suggested below:
>
> - Enabled EARLY_PCI_BRIDGE
> - Set Bridge at D:1 F:0
> - Enabled OXI PCIe952 and disabled SERIAL_PORT_ON_SUPERIO.
> Reboot Mohon Peak CRB: failed. No output. POST code at 0xA9.
>
> Will try to get further.
> If anybody has an idea...
>
> Regards,
> Patrick Agrain
>
> On Fri, 2015-03-06 at 17:25 +0100, Patrick Agrain wrote:
> >/  Hello everybody,
> />/  
> />/  Do you think that it would be possible to output the console messages
> />/  from coreboot (seabios) on another UART port (strapped to be visible on
> />/  Memory-based space or IO Space) connected on a PCIe slot ?
> />/  
> /
> Yes, it has been done before.
>
> I should have a hack for SeaBIOS to support memory-mapped UART
> somewhere, I will go and look. If I remember correctly SeaBIOS boot
> media selection only works from local keyboard, not over serial.
>
>
> >/  I've purchased a StarTech UART board with an OXPCIe952 chip, with the
> />/  same IDs as visible in ./src/drivers/uart/oxpcie.c.
> />/  
> />/  On
> />/  http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards,  
> />/  what is behind the sentence:
> />/  "In order to use the card for romstage debugging, minimal setup of the
> />/  PCIe bridge and the MPEX2S952 have to be added to romstage.c" ?
> />/  
> /
> You need to enable OxPCIe support and set EARLY_PCI_BRIDGE_* variables
> in menuconfig. If you can boot to OS with that plaform, with the serial
> card installed, get the location of PCIe rootport (aka. parent bridge)
> for OxPCIe card with lspci -vv command.
>
>
>
> Once you have OS shell, both coreboot and SeaBIOS console messages are
> available from CBMEM console using 'cbmem -c' command.
>
> >/  Thanks in advance.
> />/  Best regards,
> />/  Patrick Agrain
> />/  
> /
>
> HTH,
>
> Kyösti
>

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