[coreboot] [commit] r5958 - trunk/src/southbridge/amd/rs780

repository service svn at coreboot.org
Sun Oct 17 23:34:46 CEST 2010


Author: uwe
Date: Sun Oct 17 23:34:45 2010
New Revision: 5958
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5958

Log:
We currently read the CPU HT speed from HT chain 0's register.
Fix that to read the register from the chain where the SB chip is on.

Signed-off-by: Liu Tao <liutao1980 at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/southbridge/amd/rs780/rs780_gfx.c

Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_gfx.c	Sun Oct 17 21:30:58 2010	(r5957)
+++ trunk/src/southbridge/amd/rs780/rs780_gfx.c	Sun Oct 17 23:34:45 2010	(r5958)
@@ -304,7 +304,7 @@
 	volatile u32 * pointer;
 	int i;
 	u16 command;
-	u32 value;
+	u32 value, sblink;
 	u16 deviceid, vendorid;
 	device_t nb_dev = dev_find_slot(0, 0);
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
@@ -453,9 +453,15 @@
 	vgainfo.usMinNBVoltage = 0;
 	vgainfo.usBootUpNBVoltage = 0x1a;
 
+	/* Get SBLink value (HyperTransport I/O Hub Link ID). */
+	value = pci_read_config32(k8_f0, 0x64);
+	sblink = (value >> 8) & 0x3;
+	printk(BIOS_DEBUG, "SBLINK = %d.\n", sblink);
+
+	/* HT speed */
 	value = pci_read_config32(nb_dev, 0xd0);
 	printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
-	value = pci_read_config32(k8_f0, 0x88);
+	value = pci_read_config32(k8_f0, 0x88 + (sblink * 0x20));
 	printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
 	vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
 




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